JPH022233A - Data bus monitor system - Google Patents

Abstract

PURPOSE:To discriminate momentarily a fault of a data bus by providing a pattern generating means generating a prescribed pattern to one end of the data bus and providing a data bus fault detection means detecting the fault. CONSTITUTION:A pulse pattern repeating alternately '0' and '1' is inserted to the 10th time slot of a time slot string from a 0/1 alternate generator 30 of a printed circuit board 10-n and the result is sent to a data bus. The pulse pattern is fed to one input terminal of an Exc.OR circuit 40 provided to the printed circuit board 10-1 via the data bus. The same pulse pattern as that of the 0/1 alternate generator 30 is outputted to other input terminal of the Exc.OR circuit 40. Then the Exc.OR circuit 40 compares the both in the unit of bits. As a result, if a fault takes place in the data bus, it is detected momentarily.

Description

[Detailed Description of the Invention] [Summary] Regarding the monitoring method of a bidirectional data bus used when transmitting data between transmission devices, etc., when a fault occurs in the data bus or data, it is possible to distinguish the location of the fault. The purpose of the present invention is to provide a data bus monitoring system that can clearly monitor a data bus, and in an apparatus having an arithmetic processing circuit that transfers data to each other via a data bus and performs arithmetic processing on the data, a pattern generating means that generates a predetermined pattern is provided. A data bus failure detection means is provided at one end of the data bus, receives the output of the pattern generation means, and detects a failure when a failure occurs on the data bus. Configure to detect.

[Industrial application field]

The present invention relates to an improvement in a monitoring method for a bidirectional data bus used when transmitting data between transmission devices.

In this case, when a failure occurs in the data bus or data,
There is a need for a data bus monitoring method that can clearly distinguish the locations where failures occur.

[Conventional technology]

FIG. 4 is a block diagram of a circuit configuration of a conventional example.

In recent years, more and more transmission devices and data lines connecting the transmission devices are in the bus format, and it has therefore become necessary to monitor the status of the data bus.

As shown in FIG. 4, among the arithmetic processing circuits 1-1 to 1-n connected to the data bus and installed, for example, on a printed board, data is transferred between, for example, 1-1 and 1-2. In this case, microcomputer (hereinafter referred to as microcomputer) 2
Data was sent and received via the data bus based on control signals from.

A parity check section provided on each printed board was used to check for data errors.

[Problem to be solved by the invention]

However, in the above-mentioned circuit, when monitoring the data bus, data could only be monitored by parity checking, so there was a problem in that it was not possible to instantly determine whether the data was incorrect or whether a failure had occurred on the data bus. was there.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data bus monitoring system that can clearly distinguish the location where a failure occurs when a failure occurs in the data bus or data.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, an arithmetic processing circuit 100 that transfers data to each other via a data bus and performs arithmetic processing on the data.
-1 to 100-n, 300 is a pattern generating means that is provided at one end of the data bus and generates a predetermined pattern.

A data bus failure detection means 400 is provided at the other end of the data bus, receives the output of the pattern generation means 300, and detects a failure when a failure occurs on the data bus.

Then, when a data bus failure occurs, the failure is detected.

[For production]

In FIG. 1, a pattern generating means 300 for generating a predetermined pattern is provided at one end of a data bus to which arithmetic processing circuits 100-1 to 100-n that perform arithmetic processing of data are connected.

Furthermore, a data bus failure detection means 400 is provided at the other end of the data bus, which inputs the output of the pattern generation means 300 and detects a failure when a failure occurs in the data bus.

For example, a pattern generating means for outputting the same pattern as the output of the pattern generating means 300 is provided in the data bus failure detection means 400, and the two outputs are compared, and when they do not match, it is determined that a failure has occurred in the data bus. judge.

〔Example〕

FIG. 2 is a circuit configuration block diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing time slots used in the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In Figure 2, a printed board 1 connected to a data bus
Each of 0-2 to 10-(n-1) is provided with an arithmetic processing circuit (not shown). For example, an O/1 alternating generator 30 is provided on the printed board 10-n, and the 10-1
As a pattern checker, an O/1 alternating generator 31 and an exclusive OR circuit (hereinafter referred to as Exc or OR circuit) 40 are used.
will be established.

Then, for example, "0" and "l" are alternately repeated from the 0/1 alternating generator 30 of the printed board 10-n to, for example, the 10th time slot of the time slot sequence shown in FIG. 3(a) and (bl). A pulse pattern is inserted and sent to the data bus. This pulse pattern is applied to one input terminal of the Exc, OR circuit 40 provided on the printed board 10-1 via the data bus. The output of the 0/1 alternating generator 31 provided on the printed board 10-1, which outputs the same pulse pattern as the 0/1 alternating generator 30, is added to the input terminal. Let's compare the two.

εxc, due to the nature of the OR circuit 40, when both values fail (“0” and “0′” or “1m and “1”), it becomes 0.
”, and when the two do not match, outputs “1”. Then, when the output is “1”, an alarm is generated.

As a result, when a fault occurs on the data bus, it can be detected instantly.

shows.

〔Effect of the invention〕

As described above, according to the present invention, abnormalities in the data bus can be instantly determined. Therefore, abnormalities in data can be clearly distinguished.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram of a circuit configuration of an embodiment of the invention, and FIG. 3 is a diagram showing time slots used in the embodiment. FIG. 4 is a block diagram of a circuit configuration of a conventional example. In the figure, 300 is a pattern generation means, and 400 is a data bus fault detection means (a) (shi). Huff-mouth and nuff diagram for the prayers of the archipelago Figure 2 Figure 1 Huff-mouth and nuff diagram for each of the rows of grass pots Figure 4i

Claims (1)

[Claims] Arithmetic processing circuits (100-1 to 100-n) that transfer data to each other via a data bus and perform arithmetic processing on the data.
In the apparatus having: pattern generating means (300) for generating a predetermined pattern;
is provided at one end of the data bus, and a data bus failure detection means (400) is provided at the other end of the data bus, which inputs the output of the pattern generation means (300) and detects a failure when a failure occurs on the data bus. 1. A data bus monitoring method, characterized in that a data bus monitoring system is provided, and a fault is detected when a fault occurs in the data bus.