JPH0756977B2 - Data anomaly detection method for parallel data communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a parallel data communication system that transfers parallel data between processors or between processors and I / O devices in a bit-parallel manner, it is detected whether an error has occurred in the transferred data due to a failure. With regard to the data anomaly detection method, the parallel data string is composed of multiple bits for the purpose of surely detecting the failure even if the failure bit is fixed at "0" or "1". In a parallel data communication system in which serial parallel transfer is sequentially performed between devices via parallel signal lines, the error detection code and an inverted error detection code obtained by inverting the logic of this error detection code are added to these parallel data strings on the transmission side. Then, the data is transferred in parallel, and the receiving side is configured to detect an abnormality in the transfer data based on the error detection code and the inverted error detection code.

[Industrial application] The present invention determines whether or not an error occurs in transfer data due to a failure in a parallel data communication system that transfers parallel data in a bit-parallel manner between processors or between processors and I / O devices. The present invention relates to a data abnormality detection method for detecting.

For example, a bit parallel interface is used for data communication between processors in a device having a plurality of processors. Generally, a check using a block check character BCC (Block Check Character: exclusive OR of all data) is performed to judge whether the communication data is good or bad.
BCC may not be able to detect hardware failure. Therefore, it is necessary to be able to reliably detect any data abnormality and improve the reliability of data abnormality detection.

[Prior Art] FIG. 7 shows a system in which parallel data is transferred in parallel between two processors. In the figure, 8 parallel signal lines b0 corresponding to 8 bits of parallel data are provided between the processors 1 and 2.
To b7 are provided, the parallel data strings D1, D2, ... Dn are sequentially transferred via the signal lines b0 to b7, and finally the block detection character BCC of these parallel data strings is added and transferred. To be done.

[Problems to be Solved by the Invention] In the conventional parallel data communication system, parallel signal lines b0 to b7 are used.
Is open (1 level) or short (0 level)
When a failure occurs in Level) mode, the failure cannot be detected in the following cases.

When the faulty bit line transmits only "0" fixed data or "1" fixed data, it cannot be determined whether this is a fault.

If the number of "1" of the bit corresponding to the faulty bit is odd or even and does not always change, the fault cannot be detected even by the block check character BCC code D.

In any case, the block check character BCC may not be able to check the abnormality of the data, so it is necessary to surely detect the abnormality even in such a failure mode.

Therefore, an object of the present invention is to enable reliable fault detection even for a fault in which a fault bit is fixed at "0" or "1".

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

A method for detecting an abnormality in parallel data communication according to the present invention is a method for detecting a parallel data string via a parallel signal line 13 of a plurality of bits.
A method for detecting data anomalies in parallel data communication in which data is sequentially transferred in parallel between two error detection codes on the transmitting side for error detection of each digit of parallel data in the horizontal direction for each predetermined length of the parallel data string. The ECC and the inverted error detection code * ECC, which is the inverted logic of this error detection code ECC, are added and transferred in parallel. At the receiving side, the error detection code ECC and the inverted error detection code added to the received parallel data string. * ECC
Error detection code ECC _R and its inversion error detection code created on the receiving side from the received parallel data string
An error is detected for each digit of parallel data by comparing each digit of the parallel data with ECC _R and determining that the received data is abnormal when an error is detected by at least one of the error detection code and the inverted error detection code. Is to do.

[Action]

The conventional error detection code ECC is added to the parallel data string PDT to be transferred, and the inverted error detection code * ECC created by inverting the logic of each digit of this error detection code ECC is added and sent to the receiving side.

The receiving side creates the error detection code ECC _R and the inverted error detection code * ECC _R based on the received parallel data string PDT in the same manner as the sending side, and the error detection code added to the received parallel data string. ECC and inversion error detection code * ECC is compared with each digit of parallel data. As a result of this comparison, if no abnormality is detected by either the error detection code ECC or the reverse error detection code * ECC, the received data is judged to be normal. On the other hand, if an abnormality is detected by at least one of these, it is determined that the received data is abnormal. Since this determination is performed for each digit of the parallel data, it is possible to eventually detect a hardware abnormality of the parallel signal line 13 that transmits the parallel data for each digit. As a result, the error detection code ECC in the past may not be able to detect anomalies.
It is also possible to detect faults such as fixation.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an inter-device parallel data communication system using a data anomaly detection method of parallel data communication as an embodiment of the present invention. In the figure, 1 and 2 are processors, and between the processors 1 and 2, 8-bit parallel signal lines b0 to b
7 connected to each other.

FIG. 3 shows a format of communication data transferred between the processors 1 and 2. As shown in the figure, each data of the parallel transfer data strings D1, D2 ... Dn consists of 8-bit parallel data, and a block check character BCC is added as an error detection code at the end of these data strings D1, ... Dn. And
After that, an inverted block check character * BCC, which is the inverted logic (“1” and “0”) of each bit of the block check character BCC, is added.

FIG. 4 shows a data transfer processing procedure in the processor 1 on the data transmitting side, and FIG. 5 shows a data transfer processing procedure in the processor 2 on the data receiving side.
Hereinafter, the data abnormality detection method of the embodiment will be described with reference to these drawings.

First, in the transmission side processor 1, the transmission data string D1 ...
While sequentially setting Dn (step S2) and creating the block check character BCC of these transmission data strings D1 ... Dn (step S3), these transmission data strings D1 ... Dn are connected to the parallel signal lines b0 ... The data is sequentially transferred to the processor 2 side via b7 (steps S2 to S5).

If the transmission of all the transmission data strings D1 ... Dn is completed (step S5), next, these transmission data strings D1 ... Dn
The inversion block check character * BCC is created by inverting the logical value of each bit by the block check character BCC created from (step S6), and this block creation character BCC and the reverse block check character * BCC are shown in FIG. As shown in (1), the data is transferred to the processor 2 side after the transmission data strings D1, D2 ... Dn.

The processor 2 on the receiving side once receives all the data sent from the processor 1 on the transmitting side, including the block check character BCC and the reverse block check character * BCC (steps S12, S13), and when it is completed. , A new block check character BCC _R is created on the receiving side from the received data strings D1, D2, ... Dn (step S16), and the block check character BCC _R created on the receiving side and the processor 1 side are received. Compare with the block check character BCC to check if the data is abnormal. If there is an abnormality, the received data abnormality process is performed (step S18).

On the other hand, if no abnormality is detected by this block check character BCC, the reverse side block check character * BCC _R is created from this block check character BCC on the receiving side (step S16), and this is received from the processor 1 side. A data abnormality check is performed by comparing the reversed block check character * BCC (step S17). As a result of this check,
If there is an error, the received data error process is performed (step S1
8) If there is no abnormality, process the received data (step S
19).

In this way, not only the block check character BCC but also the reverse block check character * BCC is sent from the sending side, and the receiving side checks the data abnormality not only by the block check character BCC but also by the reverse block check character * BCC. By doing so, even if there is a hardware failure in which the failure bit of the parallel signal line is fixed at "0" or "1", this failure can be detected reliably.

For example, as shown in FIG. 2, when a failure of fixing the bit line b4 to "1" and a failure of fixing the bit line b5 to "0" occurs, the conventional data error detection only by the block check character BCC causes a failure. However, it is possible to detect a failure by using the reverse block check character * BCC together to detect a data abnormality.

FIG. 6 shows an example in which the data anomaly detection method of the present invention is applied to a multiplex terminal device of a communication system. In the figure, 11 is a multiplexed bus controller, 12 is I / O respectively.
Interface, these multiplexed bus controllers
The 11 and the I / O interface 12 are each equipped with a microprocessor, and a bus 13 is connected between them to transfer data.

Reference numeral 14 is a supervisory control unit for supervising the state of the system, and the supervisory control unit 14 and the multiplex bus controller 11 and the I / O interface 12 are connected by a supervisory control bus 15.

Here, when the I / O interface 12 of the multiplexed bus controller 11 transfers the monitoring data to the monitoring controller 14 via the monitoring control bus 15, the data abnormality detection method of the present invention described above It is used for data abnormality detection.

〔The invention's effect〕

According to the present invention, a faulty bit of a parallel signal line or the like fixed to "0" or "1" which may not be conventionally detected
It is now possible to reliably detect data anomalies caused by immobilization, etc. This can prevent serious faults from being triggered by incorrect data processing, and contributes greatly to improving system reliability.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram showing an interprocessor data communication system using a data anomaly detection method of parallel data communication as one embodiment of the present invention, and FIG. FIG. 4 is a diagram showing a format of a data string transferred in the example system, FIG. 4 is a flow chart showing a data transfer processing procedure in the transmission side processor in the embodiment system, and FIG. 5 is data transfer in the reception side processor in the embodiment system. 6 is a flow chart showing a processing procedure, FIG. 6 is a block diagram showing an application example system of the method of the present invention, and FIG. 7 is a diagram for explaining a conventional data abnormality detection method. In the figure, 1,2 ... Processor 11 ... Multiplexed bus controller 12 ... I / O interface 13 ... Bus 14 ... Monitoring controller 15 ... Monitoring control bus

Claims (1)

[Claims] 1. A data anomaly detection method for parallel data communication, wherein a parallel data string is sequentially transferred in parallel between devices (11, 12) via a multi-bit parallel signal line (13). An error detection code (ECC) for horizontally detecting an error in each digit of the parallel data and an inverted error detection code (* ECC) obtained by inverting the logic of the error detection code for each predetermined length of the parallel data string. In parallel transmission, and at the receiving side, the error detection code and the inverted error detection code added to the received parallel data sequence are respectively generated from the received parallel data sequence at the receiving side, and The parallel error detection code and the parallel data are compared for each digit, and if an error is detected by at least one of the error detection code and the reverse error detection code, it is judged that the received data is abnormal, and the parallel data is detected. Parallel communication data abnormality detecting method to perform each digit each abnormality detection data.