JPH03190333A - Data abnormality detection system for parallel data communication - Google Patents

Abstract

PURPOSE:To attain the detection of a fault surely by adding an error check code and an inverted error check code inverting the logic of the error check code to a parallel data string at the sender side, transferring the result in parallel and detecting a fault of a transfer data at a receiver side based on the error check code and the inverted error check code. CONSTITUTION:A sender side adds an error check code ECC such as a block check character BCC and an inverted error check code *ECC resulting from inverting the logic of the said error check code to a parallel data string, and transfers the result in parallel in the parallel data communication system in which the parallel data string is transferred in parallel between equipments 11, 12 via a parallel signal line 13 in plural bits. Then the receiver side detects a fault of the transfer data based on the error check code ECC and the error check code *ECC. The receiver side uses not only the error check code ECC by the inverted error check code *ECC to check the data error and the detection of a fault bit such as fixed '0' or fixed '1' is attained.

Description

[Detailed Description of the Invention] Summary] Data for detecting whether or not an abnormality has occurred in transferred data due to a failure in a parallel data communication system that transfers parallel data bit-parallel between processors or between a processor and an I10 device. Regarding the abnormality detection method.

The purpose of this invention is to ensure failure detection even for failures in which the failure bit is fixed to "O" or fixed to "1".

In a parallel data communication system in which parallel data strings are sequentially transferred in parallel between devices via multiple-bit parallel signal lines, the transmitting side uses error detection codes for these parallel data strings and inverts the logic of this error detection code. An inverted error detection code is added and transferred in parallel, and the receiving side is configured to detect an abnormality in the transferred data based on this error detection code and the inverted error detection code.

[Industrial Application Field] The present invention detects whether an abnormality has occurred in transferred data due to a failure in a parallel data communication system that transfers parallel data bit-parallel between processors or between a processor and an I10 device. Related to data anomaly detection method.

For example, a bit parallel interface is used for data communication between processors in a device having multiple processors. Block check characters BCC (Block Check C) are generally used to determine the quality of this communication data.
haracter (exclusive OR of all data) is used.

Depending on the data abnormality, this block check character BC
Even with C, hardware failures may not be detected.

Therefore, there is a need to be able to reliably detect any data anomaly and improve the reliability of data anomaly detection.

[Prior Art] FIG. 7 shows a system for transferring parallel data between two processors in parallel. In the figure, eight parallel signal lines bo-b7 corresponding to 8 bits of parallel data are provided between processors 1 and 2, and parallel data strings Di, D2, . ...Dn are sequentially transferred, and finally the block detection characters BCC of these parallel data strings are added and transferred.

[Problem to be solved by the invention] In the conventional parallel data communication system, the parallel signal line bo-
Either b7 is oven (lebel) or short (
When a failure occurs in 0 level) mode, the failure cannot be discovered in the following cases.

■The faulty bit line is fixed at “0” or °°1
If only fixed data is sent, it cannot be determined whether this is a failure or not.

■If the number of “1” bits corresponding to the fault bit is an odd or even number and does not change, the block check character BCC
No fault can be detected even with code D.

In any case, since it may not be possible to check for data abnormalities using the block check character BCC, it is necessary to be able to reliably detect abnormalities even in such failure modes.

Therefore, an object of the present invention is to enable reliable failure detection even for failures in which the failure bit is fixed at 0 or 1.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

The data abnormality detection method for parallel data communication according to the present invention is as follows:
In a parallel data communication system in which @ column data strings are sequentially transferred in parallel between devices 11 and 12 via multi-bit parallel signal lines 13, on the transmitting side, error detection codes such as block check characters BCG and ECC are added to these parallel data strings. and an inverted error detection code *ECC, which is the logic of this error detection code inverted, are added and transferred in parallel, and the receiving side detects abnormalities in the transferred data based on this error detection code ECC and inverted error detection code *ECC. configured to do so.

[Operation] The conventional error detection code E is applied to the parallel data string PDT to be transferred.
An inverted error detection code created by adding CC and further inverting the logic of each bit of this error detection code ECC *
Add ECC and send to the receiving side. On the receiving side, not only the error detection code ECC but also this inverted error detection code *E
By also using CC to detect data abnormalities, it is also possible to detect faulty bits such as fixed to °O or fixed to l.

[Example] The present invention will be described in detail below with reference to nine drawings.

FIG. 2 shows an inter-device parallel data communication system using a data abnormality detection method for parallel data communication as an embodiment of the present invention. In the figure, 1 and 2 are processors, and the processors 1 and 2 are interconnected by 8-bit parallel signal lines bO-b7.

FIG. 3 shows the format of communication data transferred between processors 1.2. As shown in the figure, each data in the parallel transfer data strings DI, D2...Dn consists of 8-bit parallel data, and these data strings DI, ...D
At the end of n, a block check character BCC is added as an error detection code, and then an inverted block check character *BCC, which is the inversion of the logic (l" and °0") of each bit of this block check character BCC, is added. be done.

FIG. 4 shows a data transfer processing procedure in the data transmitting side processor 1, and FIG. 5 shows a data transfer processing procedure in the data receiving side processor 2.

Hereinafter, the data anomaly detection method of the embodiment will be explained with reference to these drawings.

First, in the sending processor 1, the sending data string DI
-Dn are set sequentially (step S2), and while creating block check characters BCC for these transmission data strings DI -Dn (step S3), these transmission data strings D1
. . . Dn is sequentially transferred to the processor 2 side via the parallel signal line bo-b7 (steps 82 to S5).

When the transmission of all the transmission data strings Di...Dn is completed (step 55)9, next, these transmission data strings D1
... Create an inverted block check character *BCC by inverting the logical value of each bit using the block check character BCC created from Dn (step S6), and combine this block creation character BCC and the inverted block check character *BCC. Third
As shown in the figure, transmission data strings DI, D2...Dn
After that, the data is transferred to the processor 2 side.

The receiving processor 2 once receives all the data sent from the transmitting processor 1, including the block check character BCC and inverted block check character *BCC (steps S12, 513), and once this is completed, The received data string DI, D2. ...From Dn, the receiving side creates a new block check character BCCR (Step 516), and the block check character l3 created on this receiving side
The OCR is compared with the block check character BCC received from the processor I side to check whether there is any abnormality in the data. If there is an abnormality, a received data abnormality process is performed (step 518).

On the other hand, if no abnormality is detected by this block check character BCC, this block check character BCC
An inverted block check character *BCCR is created on the receiving side (step 516), and data abnormality is checked by comparing this with the inverted block check character *BCC received from the processor 1 side (step 517). As a result of this check, if there is an abnormality, the received data is processed for abnormality (step 518), and if there is no abnormality, the received data is processed (step 519).

In this way, the sending side sends not only the block check character BCC but also the inverted block check character *BCC, and the receiving side sends not only the block check character BCC but also the inverted block check character *BCC (
If data abnormalities are also checked using the inverted block check character *BCC, this problem can be avoided even if there is a hardware failure in which the failure bit of the parallel signal line is fixed to "O" or "l". It becomes possible to detect failures reliably.

For example, as shown in FIG. 2, "1" on bit line b4
If a fault occurs where bit line b5 is fixed to "0", the fault cannot be detected by conventional data abnormality detection using only the block check character BCC. By using this method to detect data anomalies, it becomes possible to detect failures.

FIG. 6 shows an example in which the data anomaly detection method of the present invention is applied to a multiplex terminal device of a communication system. In the figure, 11 is a multiplexed bus controller, 12 is an I10 interface, and each of these multiplexed bus controller 11 and I10 interface 12 is equipped with a microprocessor.
3 to perform data transfer.

Reference numeral 14 denotes a supervisory control unit for monitoring the state of this system, and a supervisory control bus 15 connects this supervisory control unit 14 to the multiplexed bus controller 11 and I10 interface 12.

Here, the data abnormality detection method of the present invention described above is as follows.

When each I10 interface 12 of the multiplexed bus controller 11 transfers monitoring data to the monitoring control section 14 via the monitoring control bus 15, it is used to detect data abnormality in the transferred data.

[Effects of the Invention] According to the present invention, it is possible to reliably detect data abnormalities caused by fixing °°O" or °l" of faulty bits in parallel signal lines, etc., which could not be detected conventionally. This makes it possible to prevent serious failures caused by erroneous data processing, and greatly contributes to improving system reliability.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing an inter-processor data communication system using a data abnormality detection method for parallel data communication as an embodiment of the present invention. FIG. 3 is a diagram showing the format of a data string transferred in the embodiment system. FIG. 4 is a flowchart showing the data transfer processing procedure in the transmitting processor in the embodiment system. FIG. 5 is a flowchart showing the data transfer processing procedure in the receiving processor in the embodiment system. FIG. 6 is a block diagram showing an example system to which the method of the present invention is applied. FIG. 7 is a diagram for explaining a conventional data abnormality detection method. In fig. 1.2... Processor 11... Multiplexed bus controller 12... I10 interface 13... Bus 14... Supervisory control section 15... Supervisory control bus

Claims (1)

[Claims] In a parallel data communication system in which parallel data strings are sequentially transferred in parallel between devices (11, 12) via multi-bit parallel signal lines (13), on the transmitting side, these parallel data strings are An error detection code (ECC) and an inverted error detection code (*ECC), which is the logic of the error detection code inverted, are added and transferred in parallel, and the receiving side receives the error detection code (ECC) and the inverted error detection code. A data abnormality detection method for parallel data communication configured to detect abnormalities in transferred data based on (*ECC).