JPH02117233A - Signal transmission path monitoring circuit - Google Patents

Signal transmission path monitoring circuit

Info

Publication number
JPH02117233A
JPH02117233A JP26956788A JP26956788A JPH02117233A JP H02117233 A JPH02117233 A JP H02117233A JP 26956788 A JP26956788 A JP 26956788A JP 26956788 A JP26956788 A JP 26956788A JP H02117233 A JPH02117233 A JP H02117233A
Authority
JP
Japan
Prior art keywords
signal
pilot signal
transmission
bit
transmission path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26956788A
Other languages
Japanese (ja)
Inventor
Shoji Matsuda
庄司 松田
Haruo Akagi
赤木 治生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Steel Works Ltd
Technical Research and Development Institute of Japan Defence Agency
Original Assignee
Japan Steel Works Ltd
Technical Research and Development Institute of Japan Defence Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Steel Works Ltd, Technical Research and Development Institute of Japan Defence Agency filed Critical Japan Steel Works Ltd
Priority to JP26956788A priority Critical patent/JPH02117233A/en
Publication of JPH02117233A publication Critical patent/JPH02117233A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To monitor the grounding and disconnection of a transmission path by transmitting to input a pilot signal consisting of 0 and 1 within the null time of a transmission signal, providing a selector and a pilot signal check circuit on a reception side, and checking the signal by the circuit. CONSTITUTION:A pilot signal generator 5 generates the pilot signal consisting of 0 and 1 within the null time in a signal transmission cycle. A switch generates signals y1-yn by inputting the pilot signal to transmission signals x1-xn, and transmits them to the transmission path via a line driver 2. On the reception side, the signal is received by a line receiver 3, and the pilot signal of each bit is taken out by the selector 7, and is sent to the check circuit 8. The check circuit 8 checks 0 and 1 of the pilot signal for each bit, and judges it as a normal signal when they are correct. When the grounding or the disconnection occurs in either transmission path, the pilot signal is received in combination of 0 and 0 or 1 and 1, therefore, a defective condition is judged for every bit.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ディジタル信号伝送路の動作を監視する信
号伝送路監視回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal transmission line monitoring circuit that monitors the operation of a digital signal transmission line.

〔従来の技術〕[Conventional technology]

第5図は、従来から一般に使用されているディジタル信
号伝送路の動作監視回路の系統図である。
FIG. 5 is a system diagram of a conventionally commonly used operation monitoring circuit for a digital signal transmission line.

この図において、1はnビットの信号Xl+xl+・・
・・・・x7に対するパリティ−・ビットX、の発生器
、2はパリティ−・ビット発生器1で発生したパリティ
−・ビットx、を含む(n+1)ビットの信号を送信す
る(n+1)個のライン・ドライバ、3はこのライン・
ドライバ2に対応する(n+1)個のライン・レシーバ
、4はパリティ−・エラーの検出器である。
In this figure, 1 is an n-bit signal Xl+xl+...
. . . A generator of parity bits X for x7, 2 is an (n+1) number of line driver, 3 is this line driver
(n+1) line receivers corresponding to driver 2; 4 is a parity error detector;

次に動作について説明する。パリティ−・ビット発生器
1はnビットの信号x、x2.・・・・・・x7に対し
奇数パリティ−または偶数パリティ−のパリティ−・ビ
ットX、を発生する。このパリティ−・ビアトx2を含
む<n+1)ビットの信号は、各々ライン・ドライバ2
により伝送路へ向けて送信される。受信側では、これら
の信号を(n+1)個のライン・レシーバ3で受信した
後、パリティ−検出器4によりパリティ−異常の有無を
判定し、伝送路の監視を行う。
Next, the operation will be explained. Parity bit generator 1 generates n-bit signals x, x2 . . . . Generates parity bit X of odd parity or even parity for x7. This <n+1) bit signal including parity viat x2 is sent to each line driver 2.
is sent to the transmission path. On the receiving side, after these signals are received by (n+1) line receivers 3, a parity detector 4 determines whether there is a parity abnormality and monitors the transmission path.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の信号伝送路監視回路は以上のように構成されてい
るので、信号の他にパリティ−・ビットを伝送しなけれ
ばならず、このための伝送路を設けなければならないと
いう欠点があった。さらに、1ビットのパリティ−・ビ
ットでは、同時に奇数本の伝送路に異常が生じた場合に
はこれを検出できるが、同時に偶数本の伝送路に異常が
生じた場合にはこれを検出できないという問題点があっ
た。
Since the conventional signal transmission path monitoring circuit is constructed as described above, it has the disadvantage that it must transmit parity bits in addition to signals, and a transmission path must be provided for this purpose. Furthermore, with one parity bit, it is possible to detect an abnormality when an odd number of transmission lines occurs at the same time, but it cannot be detected when an abnormality occurs on an even number of transmission lines at the same time. There was a problem.

この発明は上記のような問題点を解消するためになされ
たもので、個々の伝送路の接地及び断線による異常をパ
リティ−・ビット等による伝送路の追加なしに検出でき
、かつ、同時に異常となる伝送路の本数の制約なしに異
常検出が行える信号伝送路監視回路を得ることを目的と
する。
This invention was made to solve the above-mentioned problems, and it is possible to detect abnormalities due to grounding and disconnection of individual transmission lines without adding a transmission line using parity bits, etc., and to detect abnormalities at the same time. The present invention aims to provide a signal transmission line monitoring circuit that can detect abnormalities without any restrictions on the number of transmission lines.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る信号伝送路監視回路は、送信側にパイロ
ット信号発生器及び切換器を設け、伝送信号の全ビット
について信号の空き時間内にOと1からなるパイロット
信号を注入し、受信側に選択器及びパイロット信号チェ
ック回路を設け、各ビットにつきこのパイロット信号を
チェックするようにしたものである。
The signal transmission path monitoring circuit according to the present invention includes a pilot signal generator and a switching device on the transmitting side, injects a pilot signal consisting of O's and 1's for all bits of the transmitted signal during the signal idle time, and sends the pilot signal to the receiving side. A selector and a pilot signal check circuit are provided to check the pilot signal for each bit.

〔作用〕[Effect]

この発明においては、送信側で信号の空き時間内に注入
したOと1からなるパイロット信号を受信側でチェック
することにより、伝送路毎に接地及び断線の検出ができ
、しかもパリティ−・ビット等の伝送路を設ける必要が
なくなる。
In this invention, grounding and disconnection can be detected for each transmission line by checking the pilot signal consisting of O's and 1's injected during signal idle time on the transmitting side on the receiving side, and parity bit etc. There is no need to provide a transmission line.

〔実施例〕〔Example〕

以下、この発明の第1の実施例を図について説明する。 A first embodiment of the present invention will be described below with reference to the drawings.

本実施例はnビットのディジタル信号X1+X2+・・
・・・・xnの伝送路についての例である。第1図にお
いて、5は伝送周期毎にOと1からなる監視用パイロッ
ト信号を発生するバイロフト信号発生器、6は伝送信号
xl + X 2+・・・・・・x、、とパイロット信
号発生器5で発生したパイロット信号とを切換えるn個
の切換器、2はnビットの信号を送信するn個のライン
・ドライバ、3はこのライン・ドライバ2に対応するn
個のライン・レシーバ、7は各ビットの信号からバイロ
フト信号を取出すn個の選択器、8はバイロフト信号の
チェック回路である。
In this embodiment, an n-bit digital signal X1+X2+...
. . . This is an example of a transmission path of xn. In FIG. 1, 5 is a biloft signal generator that generates a monitoring pilot signal consisting of O and 1 every transmission period, 6 is a transmission signal xl + X 2+...x, and a pilot signal generator. 5, n switchers that switch between the pilot signals generated at 5, 2, n line drivers that transmit n-bit signals, and 3, n corresponding to this line driver 2.
7 is a selector for extracting a biloft signal from each bit signal, and 8 is a biloft signal check circuit.

次に、本実施例による回路の動作について、第1図に示
した系統図及び第2図に示すタイミング・チャートを参
照して説明する。nビットの伝送信号xl+Xz、・・
・・・・x7には、各々、第2図(a)に示すように、
信号伝送周期内に信号伝送期間Tsのほか、空き時間T
、が存在するものとする。パイロット信号発生器5は、
この空き時間TDの期間内に、第2図(blで示すよう
なOと1からなるバイロフト信号を発生する。切換器6
は伝送信号XI+x!、・・・・・・Xnにこのパイロ
ット信号を注入して、第2図(C)で示す信号)’l+
yz+・・・・・・y7としてライン・ドライバ2を介
して伝送路へ送信する。受信側では、この信号をライン
・レシーバ3によす受信し、選択器7により各ビットの
パイロット信号を取出す。パイロット信号のチェック回
路8は、各ビットにつきこのパイロット信号のOと1と
をチェックし、正しければ良と判定する。もし、いずれ
かの伝送路が接地または断線となれば、パイロット信号
はOとOまたは1と1という組合わせで受信されるので
、各ビット毎に不良の判定をすることができる。
Next, the operation of the circuit according to this embodiment will be explained with reference to the system diagram shown in FIG. 1 and the timing chart shown in FIG. 2. n-bit transmission signal xl+Xz,...
... As shown in Fig. 2(a), x7 has the following values:
In addition to the signal transmission period Ts within the signal transmission cycle, there is also an idle time T
Assume that , exists. The pilot signal generator 5 is
During this idle time TD, a biloft signal consisting of O and 1 as shown in FIG. 2 (bl) is generated.
is the transmission signal XI+x! , ... Injecting this pilot signal into Xn, the signal shown in Fig. 2 (C))'l+
yz+...It is transmitted to the transmission line via the line driver 2 as y7. On the receiving side, this signal is received by a line receiver 3, and a selector 7 extracts a pilot signal of each bit. The pilot signal check circuit 8 checks O and 1 of this pilot signal for each bit, and determines that it is OK if it is correct. If any transmission line is grounded or disconnected, the pilot signal is received as a combination of O and O or 1 and 1, so it is possible to determine whether each bit is defective.

なお、上記実施例では監視用パイロット信号としてOと
1のパターンの例を示したが、これはOと1が少なくと
も1個以上あればよく、例えばlと0,0と1と0等の
パターンでも上記実施例と同様の効果があることは言う
までもない。
In addition, in the above embodiment, an example of a pattern of O and 1 was shown as a monitoring pilot signal, but this only requires at least one O and 1, and for example, a pattern of l and 0, 0, 1 and 0, etc. However, it goes without saying that the same effect as in the above embodiment can be obtained.

次に、本発明の第2の実施例について図を用いて説明す
る。第3図はこの第2の実施例による回路の構成を示す
系統図であり、図中、9.10は各々0.1からなるパ
イロット信号の発生器、11は0と1のパイロット信号
を切換える切換器、6は伝送信号とパイロット信号を切
換えるn個の切換器、2はn個のライン・ドライバ、3
はn個のライン・レシーバ、7は伝送された信号からバ
イロフト信号を取り出すn個の選択器、8はパイロット
信号のチェック回路である。
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a system diagram showing the configuration of the circuit according to the second embodiment. In the figure, 9.10 is a generator of pilot signals each consisting of 0.1, and 11 is a generator for switching pilot signals of 0 and 1. switch; 6, n switchers for switching transmission signals and pilot signals; 2, n line drivers; 3;
are n line receivers, 7 is n selectors for extracting biloft signals from the transmitted signals, and 8 is a pilot signal check circuit.

以下、本実施例による回路の動作について第3図に示し
た系統図及び第4図に示すタイミング・チャートを用い
て説明する。本実施例は伝送周期毎にOと1のパイロッ
ト信号を交互に注入する例である。0からなるパイロッ
ト信号の発生器9と、■からなるパイロット信号の発生
器10の出力は、切換器11で伝送周期毎に交互に切換
えられる。
The operation of the circuit according to this embodiment will be explained below using the system diagram shown in FIG. 3 and the timing chart shown in FIG. 4. This embodiment is an example in which O and 1 pilot signals are alternately injected every transmission period. The outputs of the pilot signal generator 9 consisting of 0 and the output of the pilot signal generator 10 consisting of 2 are alternately switched by a switch 11 every transmission period.

このパイロット信号は、切換器6により伝送信号の空き
時間T。内に注入され、ライン・ドライバ2を経て伝送
路へ出力される。受信側ではこの信号はライン・レシー
バ3で受信され、選択器7によりパイロット信号が抽出
され、パイロット信号チェック回路8で各ビットにつき
接地及び断線のチェックが行われる。
This pilot signal is transferred to the transmission signal idle time T by the switching device 6. The signal is injected into the line driver 2 and output to the transmission line. On the receiving side, this signal is received by a line receiver 3, a pilot signal is extracted by a selector 7, and a pilot signal check circuit 8 checks each bit for grounding and disconnection.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る信号伝送路監視回路によ
れば、送信側にパイロット信号発生器及び切換器を設け
、伝送信号の空き時間内にOと1からなるパイロット信
号を注入し、受信側に選択器及びパイロット信号チェッ
ク回路を設け、このパイロット信号をチェックするよう
に構成したので、パリティ−・ビット等の伝送路を付加
することなく伝送路1本1本の接地及び断線の監視を行
うことができるという効果がある。
As described above, according to the signal transmission path monitoring circuit according to the present invention, a pilot signal generator and a switching device are provided on the transmitting side, a pilot signal consisting of O's and 1's is injected during the free time of the transmitted signal, and the Since a selector and a pilot signal check circuit are installed on the side and configured to check the pilot signal, grounding and disconnection of each transmission line can be monitored without adding transmission lines such as parity bits. The effect is that it can be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の第1の実施例による信号伝送路監視
回路を示す系統図、第2図はその動作説明のためのタイ
ミング・チャートを示す図、第3図はこの発明の第2の
実施例による信号伝送路監視回路を示す系統図、第4図
はその動作説明のためのタイミング・チャートを示す図
、第5図は従来の信号伝送路監視回路を示す系統図であ
る。 lはパリティ−・ビット発生器、2はライン・ドライバ
、3はライン・レシーバ、4はパリティ−・エラー検出
器、5はOと1からなるパイロット信号発生器、6はn
個の切換器、7はn個の選択器、8はパイロット信号チ
ェック回路、9はOからなるパイロット信号発生器、1
0は1からなるパイロット信号発生器、11は切換器で
ある。 なお図中同一符号は同−又は相当部分を示す。 特許出願人 防衛庁技術研究本部長 筒井 良三第2図 第4図
FIG. 1 is a system diagram showing a signal transmission line monitoring circuit according to a first embodiment of the present invention, FIG. 2 is a diagram showing a timing chart for explaining its operation, and FIG. FIG. 4 is a system diagram showing a signal transmission path monitoring circuit according to an embodiment, FIG. 4 is a diagram showing a timing chart for explaining its operation, and FIG. 5 is a system diagram showing a conventional signal transmission path monitoring circuit. l is a parity bit generator, 2 is a line driver, 3 is a line receiver, 4 is a parity error detector, 5 is a pilot signal generator consisting of O and 1, 6 is n
7 is a selector, 8 is a pilot signal check circuit, 9 is a pilot signal generator consisting of O, 1
0 is a pilot signal generator consisting of 1, and 11 is a switch. Note that the same reference numerals in the figures indicate the same or equivalent parts. Patent applicant: Ryozo Tsutsui, Director General, Technology Research Headquarters, Defense Agency, Figure 2, Figure 4

Claims (1)

【特許請求の範囲】[Claims] (1)1ビットまたは複数ビットのディジタル信号を伝
送する回路の動作を監視する信号伝送路監視回路におい
て、 送信側に、0と1からなる監視のためのパイロット信号
を発生するパイロット信号発生器と、伝送信号の空き時
間内に該パイロット信号を注入して送信するための切換
器とを備え、 受信側に、送信された信号から上記パイロット信号を取
出すための選択器と、該パイロット信号をチェックする
パイロット信号チェック回路とを備えたことを特徴とす
る信号伝送路監視回路。
(1) In a signal transmission path monitoring circuit that monitors the operation of a circuit that transmits a 1-bit or multiple-bit digital signal, a pilot signal generator that generates a pilot signal for monitoring consisting of 0s and 1s is installed on the transmitting side. , a selector for injecting and transmitting the pilot signal during the idle time of the transmission signal, and a selector for extracting the pilot signal from the transmitted signal on the receiving side, and a selector for checking the pilot signal. 1. A signal transmission path monitoring circuit comprising a pilot signal check circuit.
JP26956788A 1988-10-27 1988-10-27 Signal transmission path monitoring circuit Pending JPH02117233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26956788A JPH02117233A (en) 1988-10-27 1988-10-27 Signal transmission path monitoring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26956788A JPH02117233A (en) 1988-10-27 1988-10-27 Signal transmission path monitoring circuit

Publications (1)

Publication Number Publication Date
JPH02117233A true JPH02117233A (en) 1990-05-01

Family

ID=17474161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26956788A Pending JPH02117233A (en) 1988-10-27 1988-10-27 Signal transmission path monitoring circuit

Country Status (1)

Country Link
JP (1) JPH02117233A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006075468A (en) * 2004-09-13 2006-03-23 Samii Kk Game machine inspection device and game machine

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224360A (en) * 1984-04-23 1985-11-08 Mitsubishi Electric Corp Signal input device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224360A (en) * 1984-04-23 1985-11-08 Mitsubishi Electric Corp Signal input device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006075468A (en) * 2004-09-13 2006-03-23 Samii Kk Game machine inspection device and game machine
JP4636529B2 (en) * 2004-09-13 2011-02-23 サミー株式会社 Gaming machine inspection device and gaming machine

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