JP2734859B2 - Communication path switching device - Google Patents

Communication path switching device

Info

Publication number
JP2734859B2
JP2734859B2 JP3981292A JP3981292A JP2734859B2 JP 2734859 B2 JP2734859 B2 JP 2734859B2 JP 3981292 A JP3981292 A JP 3981292A JP 3981292 A JP3981292 A JP 3981292A JP 2734859 B2 JP2734859 B2 JP 2734859B2
Authority
JP
Japan
Prior art keywords
data
communication path
parity
path switching
transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3981292A
Other languages
Japanese (ja)
Other versions
JPH05244124A (en
Inventor
健 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP3981292A priority Critical patent/JP2734859B2/en
Publication of JPH05244124A publication Critical patent/JPH05244124A/en
Application granted granted Critical
Publication of JP2734859B2 publication Critical patent/JP2734859B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はデジタル通信に利用す
る。特に、系交絡機能を有する通話路の切替監視技術に
関する。
The present invention is used for digital communication. In particular, the present invention relates to a communication path switching monitoring technology having a system confounding function.

【0002】[0002]

【従来の技術】2重化された通話路の系切替えは、送信
側両系から受け取るACT/SBY(Active/S
tandby)信号により受信側が生成する系選択信号
により系切替えを行い、この系切替信号を監視すること
により系切替えの正常性の保証を行っていた。
2. Description of the Related Art System switching of a duplex communication channel is performed by ACT / SBY (Active / S) received from both transmission side systems.
In this case, system switching is performed by a system selection signal generated by the receiving side in response to a (standby) signal, and normality of system switching is guaranteed by monitoring the system switching signal.

【0003】[0003]

【発明が解決しようとする課題】この方式では、系選択
信号によって実際に受信データを選択する装置に異常が
ある場合は系切替えの正常性が保証されない。
In this system, the normality of the system switching cannot be guaranteed if there is an abnormality in the device that actually selects the reception data by the system selection signal.

【0004】本発明は、このような背景に行われたもの
であり、切替直後に受信データのパリティをチェックす
ることにより、正常に系選択が行われたかを監視できる
通話路系切替装置の提供を目的とする。
The present invention has been made in view of such a background, and provides a communication path switching apparatus capable of monitoring whether or not the system has been properly selected by checking the parity of received data immediately after switching. With the goal.

【0005】[0005]

【課題を解決するための手段】本発明は、系交絡を有し
2重化された通話路にデータを送出するドライバをそれ
ぞれ含む2系統の送信側装置と、この送信側装置からの
2系統のデータを受信するレシーバと、このレシーバか
らの前記データを選択するセレクタとをそれぞれ含む2
系統の受信側装置とを備えた通話路系切替装置におい
て、前記送信側装置は、切替直後にこの2系統の通話路
にそれぞれ逆論理のパリティビットを付加した信号を送
信させる手段を備え、前記受信側装置は、受信した前記
データのパリティ論理をチェックする手段を備えたこと
を特徴とする。
According to the present invention, there are provided two transmission apparatuses each including a driver having a system confound and transmitting data to a duplex communication path, and two transmission apparatuses from the transmission apparatus. And a selector for selecting the data from the receiver.
A communication path switching device including a receiving apparatus of a system, wherein the transmitting apparatus includes a unit that transmits a signal to which a parity bit of reverse logic is added to each of the two communication paths immediately after switching, The receiving side device is provided with means for checking a parity logic of the received data.

【0006】[0006]

【作用】本発明の通話路系切替装置は、系交絡を持つ通
話路において、送信側で送信データに両系が互いに異な
る論理(ODDとEVEN)のパリティビットを付加
し、受信側で送信側両系から受け取るACT/SBY信
号により生成する系選択信号に同期して受信データの系
選択とパリティチェックの論理選択を同時に切替えるこ
とにより、系切替えの正常性を監視する。
According to the present invention, the communication path switching device of the present invention adds parity bits of different logics (ODD and EVEN) to transmission data on the transmission side and transmission side on the transmission side in a communication path having system confounding. The normality of the system switching is monitored by simultaneously switching the system selection of the received data and the logic selection of the parity check in synchronization with the system selection signal generated by the ACT / SBY signal received from both systems.

【0007】[0007]

【実施例】本発明実施例の構成を図1を参照して説明す
る。図1は本発明実施例の構成図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of an embodiment of the present invention.

【0008】本発明は、系交絡を有し2重化された通話
路にデータを送出するドライバ2および2′をそれぞれ
含む2系統の送信側装置15および15′と、この送信
側装置15および15′からの2系統のデータを受信す
るレシーバ4および4′と、このレシーバ4および4′
からの前記データを選択するセレクタ6および6′とを
それぞれ含む2系統の受信側装置16および16′とを
備えた通話路系切替装置において、送信側装置15およ
び15′は、切替直後にこの2系統の通話路にそれぞれ
逆論理のパリティビットを付加した信号を送信させる手
段としてのパリティ発生回路1および1′を備え、受信
側装置16および16′は、受信した前記データのパリ
ティ論理をチェックする手段としてのパリティチェック
回路7および7′を備えたことを特徴とする。
According to the present invention, there are provided two transmitting side devices 15 and 15 'each including drivers 2 and 2' for transmitting data to a duplex communication path having system confounding, and the transmitting side devices 15 and 15 ' Receivers 4 and 4 'for receiving the two systems of data from 15', and receivers 4 and 4 '
In the communication path switching device including two receiving devices 16 and 16 'each including selectors 6 and 6' for selecting the data from the communication devices, the transmitting devices 15 and 15 ' Parity generating circuits 1 and 1 'are provided as means for transmitting a signal having a parity bit of reverse logic added to each of the two communication paths, and the receiving devices 16 and 16' check the parity logic of the received data. And parity check circuits 7 and 7 '.

【0009】次に、本発明実施例の動作を図1および図
2を参照して説明する。図2は本発明実施例の動作を示
すフローチャートである。
Next, the operation of the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

【0010】0系および1系の送信データから送信側C
PU9および9′は切替命令を受ける(S0およびS
1)。0系パリティ発生回路1および1系パリティ発生
回路1′で8ビットのデータに互いに逆論理のパリティ
を付加し(S2)、9ビットの通話路データ10をドラ
イバ2および2′を介してレシーバ4および4′に送信
する。受信側装置16および16′の系選択回路8およ
び8′はACT/SBY信号12により系選択信号14
および14′を生成し、セレクタ6および6′、パリテ
ィチェック回路7および7′の切替えを実行する(S
3)。さらに、パリティチェック回路7および7′はパ
リティ論理をチェックする(S4)。この時、パリティ
チェックで異常が発生すれば受信側CPU3および3′
は、受信側装置16および16′の系選択系統の異常と
判断し、異常検出信号を出力する(S6)。
[0010] From transmission data of system 0 and system 1 to transmission side C
PUs 9 and 9 'receive the switching instruction (S0 and S').
1). The 0-system parity generation circuit 1 and the 1-system parity generation circuit 1 'add parity of opposite logic to the 8-bit data (S2), and the 9-bit communication path data 10 is transmitted to the receiver 4 via the drivers 2 and 2'. And 4 '. The system selection circuits 8 and 8 'of the receiving-side devices 16 and 16' receive the system selection signal 14
And 14 ', and switches the selectors 6 and 6' and the parity check circuits 7 and 7 '(S
3). Further, the parity check circuits 7 and 7 'check the parity logic (S4). At this time, if an error occurs in the parity check, the receiving CPUs 3 and 3 '
Determines that the system selection system of the receiving-side devices 16 and 16 'is abnormal, and outputs an abnormality detection signal (S6).

【0011】このように、系選択信号14および14′
によりセレクタ6および6′が切替えられた後に、パリ
ティチェック回路7および7′のチェック結果を監視し
て系切替えの正常性が確認される。
Thus, the system selection signals 14 and 14 '
After the selectors 6 and 6 'are switched, the check results of the parity check circuits 7 and 7' are monitored to confirm the normality of the system switching.

【0012】[0012]

【発明の効果】最終的にパリティ論理をチェックして系
切替えをチェックしているので、系切替障害検出能力が
向上し、結果的にシステム全体の信頼性の向上に寄与す
る。
Since the parity switching is finally checked by checking the parity logic, the system switching fault detection capability is improved, and as a result, the reliability of the entire system is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明実施例の構成図。FIG. 1 is a configuration diagram of an embodiment of the present invention.

【図2】本発明実施例の動作を示すフローチャート。FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1、1′パリティ発生回路 2、2′ドライバ 3、3′受信側CPU 4、4′レシーバ 6、6′セレクタ 7、7′パリティチェック回路 8、8′系選択回路 9、9′送信側CPU 10 0系通話データ 11 1系通話データ 12 0系ACT/SBY信号 13 1系ACT/SBY信号 14、14′系選択信号 15、15′送信側装置 16、16′受信側装置 1, 1 'parity generation circuit 2, 2' driver 3, 3 'reception side CPU 4, 4' receiver 6, 6 'selector 7, 7' parity check circuit 8, 8 'system selection circuit 9, 9' transmission side CPU 100 system communication data 11 system 1 communication data 12 system 0 ACT / SBY signal 13 system 1 ACT / SBY signal 14, 14 'system selection signal 15, 15' transmission side device 16, 16 'reception side device

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 系交絡を有し2重化された通話路にデー
タを送出するドライバをそれぞれ含む2系統の送信側装
置と、この送信側装置からの2系統のデータを受信する
レシーバと、このレシーバからの前記データを選択する
セレクタとをそれぞれ含む2系統の受信側装置とを備え
た通話路系切替装置において、 前記送信側装置は、切替直後にこの2系統の通話路にそ
れぞれ逆論理のパリティビットを付加した信号を送信さ
せる手段を備え、 前記受信側装置は、受信した前記データのパリティ論理
をチェックする手段を備えたことを特徴とする通話路系
切替装置。
1. Two systems of transmitting devices each including a driver having system confounding and transmitting data to a duplex communication channel, a receiver for receiving two systems of data from the transmitting device, And a selector for selecting the data from the receiver. The communication path switching device includes two receiving apparatuses each including a selector for selecting the data from the receiver. A communication path switching device, comprising: means for transmitting a signal to which the parity bit has been added; and wherein the reception-side apparatus has means for checking a parity logic of the received data.
JP3981292A 1992-02-26 1992-02-26 Communication path switching device Expired - Lifetime JP2734859B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3981292A JP2734859B2 (en) 1992-02-26 1992-02-26 Communication path switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3981292A JP2734859B2 (en) 1992-02-26 1992-02-26 Communication path switching device

Publications (2)

Publication Number Publication Date
JPH05244124A JPH05244124A (en) 1993-09-21
JP2734859B2 true JP2734859B2 (en) 1998-04-02

Family

ID=12563384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3981292A Expired - Lifetime JP2734859B2 (en) 1992-02-26 1992-02-26 Communication path switching device

Country Status (1)

Country Link
JP (1) JP2734859B2 (en)

Also Published As

Publication number Publication date
JPH05244124A (en) 1993-09-21

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