JPS607239A - Data transmission interface - Google Patents

Abstract

PURPOSE:To cope with an error with less number of hardware by taking notice of points that physical disconnection of a transmission line, the damage of a connector pin, and loose contact, etc. being the cause of fault of a transmission line seldom occur in all transmission lines. CONSTITUTION:When the titled interface is used for the interface of a transmitter, a parity 1-bit is added to a data in N-bit and the data is transmitted to a normal transmission line and the data in n-bit selected by a selector 62 is transmitted to a redundancy transmission line. The diagnosis by the interface is conducted by transmitting all bit patterns from a transmission side to a normal input/output line, comparing the transmitted data with the reception data received at a reception side thereby detecting a faulty line. A host processor informs a faulty line requiring changeover to each managing processor. The managing processor transmits a line changeover control signal to a transmission/reception interface through the notice of the faulty line, each transmission/reception interface executes the line and changes over the faulty line to the redundancy line.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to the configuration of an interface that eliminates fault lines in data transmission and reception.

(Prior Art) In a conventional digital signal processing system, a data transmission path (here, a transmission path) connects a signal processing device.
It consists of physical transmission lines and connectors, and electrical interfaces such as line drivers and receivers. ) had a configuration as shown in Figure 1.

That is, there is a line between device 1 and device 2 shown in the figure.
Transmission lines 3 and 4 consisting of a driver/receiver 5, a connection connector 6, and a transmission line 7 are provided in parallel, and both ends thereof are connected to electrical switching devices 8 and 9 of the devices 1 and 2, so-called transmission lines. A full-duplex configuration was adopted.

According to the full-duplex configuration of the transmission line, transmission lines 3 and 4
If a failure occurs in either one of the threads, the system can be quickly restored by switching to the other thread.
The drawback was that the amount of hardware increased due to full duplex.

(Objective of the Invention) The present invention has been made to solve the above-mentioned drawbacks, and the causes of transmission line failures include physical disconnection of transmission lines, electrical deterioration of line drivers, receivers, etc., and connections. Focusing on the fact that damage to connector pins and loose contacts are extremely rare occurrences in all transmission lines,
The purpose of this invention is to provide a data transmission interface configuration that can handle failures with less hardware.

(Structure of the Invention) The structure of the present invention has N normal lines and n redundant lines (2≦n<N) in the transmission path between the transmitting section and the receiving section that perform multi-bit parallel digital transmission. 17. Means for switching a desired line among the normal lines to a redundant line, and means for detecting a fault in the normal line, wherein the fault detection means controls the switching means by detecting a fault, and the normal line is switched to a redundant line. This system is characterized in that a faulty line in the line is switched to the redundant line.

(Embodiment) FIG. 2 is a block diagram showing the configuration of the transmitting/receiving unit according to the embodiment of the present invention, in which 10 is an N-bit parallel input terminal on the transmitting/receiving unit side, and 1 is an N-bit parallel input terminal connected to 30 and IO. Connection line 12 is an N-bit parallel connection line connecting 20 and 10, 2
0 is the noise generation mechanism, 21 is the 1-bit parity output line of 20, 3θ is the selector, 31 is the selector control line of 30, 32 is the N+1 bit parallel output line of 30, 40 is N
]-1 bit buffer register, 4 is 40 N+]
+1 bit medium output line connected to 50.60, 50 is N+1 bit parallel connection line connecting 41 and 51, 51 is connection terminal with N+1 bit parallel normal transmission line, 60 is 61
N+1 bit parallel connection line connecting and 41, 61 is 62
N-1-1 bit parallel input line, 62 is a selector, 63
is the selector control line of 62, 64 is the n-bit parallel output line of 62 and is connected to 70, 70 is the connection terminal with the n-bit parallel redundant transmission line, 8θ is the N+1 bit parallel connection line that connects 5 and 81. , 81 is a line switch, 82 is 70 and 8
n-bit parallel redundant connection line connecting 1, 83 is N of 81
+1 bit parallel output line, 84 is the switching control line of 81, 90
is the N+1 bit parallel connection line connecting 60 and 93, 9 is the N bit parallel connection line connecting 90 and 92, 92 is the N bit parallel data output terminal on the transmitting/receiving device side, 93 is 94
The N+1 bit parallel input connection line, 94 is a spear error notification line, and 95 is an /F error notification line.

First, a case where this device operates as an interface between a transmitting device and a transmission path will be described. N-bit parallel data sent from the transmitting device is input from the input terminal 10 of the device. The data inputted from the input terminal 10 is branched to the connection line 12 which is in contact with the connection line 1, and is connected to the connection line 1.
The N-bit parallel data on 2 is input to the 01J tee generation mechanism 20, and the 1 bit ye IJ tee bit is
Output to parity output line 2. On the other hand, the N-bit parallel data is input to the selector 30 via the connection line 11, and the 1-bit d' parity bit is input to the selector 30 via the parity output line 21), and the data is input via the selector control line 3. The parity bit is selected and output to the output line 32 of the selector 30 as N+1 bit parallel data.

The N+1 bits of data (N bits of input data, 1 bit of parity bit) on output line 32 are outputted to output line 4 of 40 via buffer register 40. The data on the output line 4 is sent via the connection line 50 to the connection terminal 51 with the N+l bit normal transmission path.

On the other hand, the normal N+1 bit data is the connection line 60.61
It becomes an input to the selector 62 via.

The selector 62 selects n lines designated by the selector control line 63 from among the N,11 input lines 61. The data of the selected n mainlands is sent to the terminal 7θ via the output line 64 as n-bit output data of the selector 62. The terminal 7o is composed of n-bit parallel lines and is a terminal connected to an n-bit parallel data redundant transmission path. As described above, when this device is used for the ink face of a transmitting device, it adds 1 parity bit to N-bit data and sends it to the regular transmission path.
Among the bits, n bits of data selected by the selector 62 can be sent to the redundant transmission path.

Next, a case where this device operates as an ink face between a receiving device and a transmission path will be described. As in the case of the transmitting device described above, the terminal 51 is connected to the regular transmission path, and the terminal 7θ is connected to the redundant transmission path. N+1-bit parallel data transmitted from the transmitter side via a regular transmission path is input to the terminal 5, and is input to the electrical line switch 8 via the connection line 80. On the other hand, the n-bit manual data at the terminal 70 is input to the line switch 8 via a redundant connection line 82. The line switching device 81 is a line switching device having a function of switching 81 input lines, up to a maximum of n designated by the switching control line 84, among the N+1 connection lines 80, to the redundant connection line 82. .

An example of the configuration of the line switch 81 is shown in FIG.

'o r1+ , 121..., 7N is shown in Figure 2
Input terminals of the line switch connected to the regular transmission line via the connection line 80 inside, 20 + 21 + 22 +...
..., 2ni is the input terminal of the line switch connected to the redundant connection line 82 in FIG. 2, 3o, 31, ...
・r3N is a selector, 40 s41 +42 +...
... + 4N is selector control line, 50 r 51 +
52 +..., 5N are output terminals of each selector.

The selector 30 has terminals 1°+20+21+...

Among the signals input from 2o-1, only one signal specified by the 1 selector control line 40 is selected, and 1i
+ 20 + 21 +..., 2n, only one signal designated by the selector control line 41 is output to the output terminal 51. Similarly, selector 4N connects terminal IN+20 . 21t...
.

Among the signals input from 2n-1, selector control line 4N
Only one signal specified by is output to the output terminal 5N. According to the above explanation, this line switch has terminals 10 and 1.
1,1□,...+IN Connect the transmission line of the regular transmission line to terminal 20'+21+...
・.

It is possible to electrically switch to any of the transmission lines of the redundant transmission lines connected to 2n-1 via the sectors 30r31+, 3N.

By passing the line switch 81 mentioned above, N -1-
Up to n lines out of the one connecting line 80 are switched to redundant connecting lines 82, and N+1 of the line switch
It is electrically connected to the output line 83 of the book. The output line 83 of the line switch is connected to the selector 300A power. The output line 83 is selected by the selector control line 31 and electrically connected to the output line 32 of the selector 30. The signal on connection line 32 is sent out on connection line 90 via 40, 41.60. The signal configuration on the connection line 90 is an N-bit parallel data section and a 1-bit error bit section, of which only the N-bit data section is transmitted via the N-bit parallel connection line 9. It is sent to the output terminal 92 of the device. On the other hand, the N+1 bit data on 90 is branched onto a connecting line 93 and input to a f IJ transmission mechanism 94 . The 94 detects a parity error in the N+1 parallel data on the 93 and outputs information on the presence or absence of an error to a parity error notification line 95.

As described above, when this device is used as an interface for a receiving device, it switches the known maximum of n transmission lines out of the N'-1 transmission lines that constitute the normal transmission line to redundant transmission lines. Data can be input. At the same time, IP integrity errors in input data can be detected and notified.

Next, detection of a fault line and control of the line switching device will be explained using FIG.

FIG. 4 is a schematic diagram showing the configuration of the control means of the line switching device according to the embodiment of the present invention.

The fact that when a fault occurs in a normal input/output line, the fault is detected as a parity error in the parity check mechanism of this transmitting/receiving interface is the same as described using FIG. 2. This parity error is notified from the transmitter/receiver ink face shown in FIG. 4 to the management processor that manages the transmitter/receiver interface through the parity error notification line.

・The management processor that has been notified of the error will notify the other side's ink interface of the occurrence of the fault through the host processor, and will cooperate with the host computer and the other side's interface to diagnose the interface in order to detect the fault line. Execute with.

This diagnosis detects faulty lines by transmitting all bit patterns from the transmitting side to normal input/output lines and comparing this transmitted data with the received data received at the receiving side. do.

A faulty line is detected through the above-described diagnosis, and the host processor notifies each management processor of the faulty line that requires switching. With this fault line notification, management 70
The processor sends line switching control signals to the transmitting and receiving interfaces, and each transmitting and receiving interface can perform line switching 2 and switch the faulty line to the redundant line.

As described above, in the embodiment, since a means for detecting the presence or absence of a fault in the transmission line is built-in, it is possible to constantly monitor the fault in the transmission line. Furthermore, when a faulty line in the regular transmission line is detected, there is a means for electrically switching any number of faulty lines within n of the transmission lines making up the normal transmission line to a redundant transmission line making up the redundant transmission line. Because of this, there are fewer transmission lines...
It is possible to provide a means for configuring a transmission line with sufficiently high operability for practical use only by adding the amount of hardware. In addition, since there are actually few machines in which a failure occurs in all the transmission lines that constitute a regular transmission line, it is practically sufficient to have only a few redundant lines as the number of redundant lines that constitute a redundant line.

(Effects of the Invention) As described above in detail using the embodiments, according to the present invention, it is possible to provide a data transmission interface configuration that can cope with failures with less hardware.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of conventional data transmission, FIG.
FIGS. 3 and 4 are block diagrams illustrating the configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Transmitter/receiver side input terminal, 20... Parity generation mechanism, 30... Selector, 31... Selector control line, 40... Bufferless star, 51... Connection terminal with normal transmission path , 62... Selector, 63... Selector control line, 70... Connection terminal with redundant transmission line, 81
...Line switching device, 84...Line switching control line, 92
...Transmitting/receiving device side output terminal, 94...f IJ tee check mechanism, 95..., O property notification line. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] In the transmission path between the transmitter and the receiver that perform multi-bit parallel digital transmission, there are N normal lines and 5 lines (2≦n<N
), and includes means for switching a desired line among the normal lines to a redundant line, and means for detecting a fault in the normal line, and the fault detecting means detects a fault to A data transmission interface characterized in that the switching means is controlled to switch the faulty line among the normal lines to the redundant line.