JPS6040224B2 - Abnormality detection device in synchronous communication control equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality detection device in a communication control device that performs data communication using a synchronization modem device.

In a synchronous communication control device of the type that assembles and disassembles signal bits using a data signal and a timing signal, if the timing signal is missing, transmission and reception become impossible.

That is, in this method, upon reception, as shown in FIG.
from each signal line, read the received data RD at each falling edge of the timing signal RT, and read the received data RD at each falling edge of the timing signal RT.
Data is output (assembles bits of received data), and during transmission, transmit data SD is sent to the modem at each rising edge of the transmit element timing signal ST, but if an abnormality occurs in these timing signals, normal data communication cannot be guaranteed. Not done. In particular, when these timing signals stop, the bit assembly or bit disassembly circuit does not operate, so data is not transmitted or received, resulting in a line hang condition. Therefore, conventional communication control devices detect the stoppage of the reception timing signal by monitoring the time of each character processing request issued to the program or by detecting a carrier disconnection from the modulation/demodulation device.

That is, in the former case, the bits are coarsened by a timing signal, and when the number of bits reaches, for example, 8 bits, a character processing request is issued to the program. Normally, the time interval at which this character processing request is raised is within a predetermined time. However, if the bit assembly does not proceed as planned due to an abnormality in the timing signal, the above-mentioned interval becomes abnormally long, and if this is detected, the abnormality in the timing signal can be known. In the latter case, the modem sends a carrier detect signal CD to the communication control device CCS, but if the modem is abnormal, for example, the power is cut off, this CD signal will also disappear, so you can receive it by watching this CD signal. Missing timing signals can be detected. In this case, it is considered to continue bit assembly using the CCU's built-in clock as a timing signal to avoid hang-ups, but there is a discrepancy when the timing signal is cut (the clock and the receiving element timing signal are different). (because it is asynchronous) it tends to cause bit errors. In addition, in this method, the timing signal is automatically switched, and if the receiving element timing signal is normal (changes normally), switching is not performed, so even if there is a bit error, it does not matter what the cause is. It is unclear whether the problem occurred and it takes a lot of time to investigate the cause. In addition, in the above-mentioned time monitoring method, it is necessary to incorporate a processing step to perform the time monitoring into the program, and the time monitoring operation requires time. Furthermore, since there are various communication speeds, the monitoring time must be adjusted according to the speed. If all of this were to be controlled by a program, the program would become too complex, so the setting of the timer value corresponding to the communication speed would have to be done by hardware, which would lead to an increase in the amount of hardware. Furthermore, since it is not possible to detect carrier interruption on the transmitting side, the method relies exclusively on time monitoring. The present invention directly detects the presence or absence of a timing signal and immediately notifies the program if the timing signal is lost.

In this way, there is no need to wait until one byte is constructed (actually longer, with some extra time);
, 2 bits, it is possible to detect the timing signal loss in a short time. It can also be used on both the transmitting side and the receiving side, and can be shared by both in the case of half-duplex communication. Next, this will be explained in detail with reference to the embodiment shown in FIG. In FIG. 2, 1 is a clock for detecting an abnormality in each timing signal 2 of the receiving element or the transmitting element, and has a frequency four times or more that of the signal 2.

Since the frequency of the timing signal 2 changes depending on the communication speed, the frequency of the clock should be at least four times the frequency of the signal 2 for the highest expected communication speed. Flip-flops '3 and 4 read the timing signal 2 or the Q output of the flip-flop 3 at the timing of the clock 1. 5
is an exclusive OR (EOR) gate which receives the Q output of flip-flop 4 and the Q output of flip-flop 3, and produces an output of 1 when they do not match and 0 when they match.

6 is a counter and ku.

It counts 1 and is reset when the "0" output of EOR5 is received at the parallel enable terminal PE. 7 is a flip-flop for raising an abnormality detection flag, and 12 is an OR gate.

The operation of this circuit will be explained with reference to FIG. 3. If clock 1 and timing signals 2 are 1 and 2 in FIG. The output is 3, 3 in FIG. 3, and the output of the flip-flop 4 is 4 in the same figure.

On the day of timing signal 2, flip-flop 3 is activated at the L switching point.
The Q output of the flip-flop 4 and the Q output of the flip-flop 4 both become H level, and the output of the EOR 5 becomes ``0'', resetting the counter 6. The number of bits of the counter 6 is determined by the frequency ratio of the timing signal 2 and the clock signal, and the frequency ratio of the timing signal 2 and the clock. In the example, if the value is 4 or more, the counter 6 will be reset before it overflows.On the other hand, if the timing signal 2 is fixed at the H level as shown by the dotted line, the Q output of the flip-flop 3 will be L, The Q output of the flip-flop 4 is H, so the output of the EOR 5 is "1", that is, the state of not being reset continues for more than 4 clocks, and the counter 6 overflows.If the timing signal 2 is fixed at the L level is the same, and this timing signal is H
Alternatively, since the fact that L' is fixed means that the timing signal is stopped, the presence or absence of the timing signal 2 can be detected by these 3 to 6 circuits. Furthermore, the timing signal abnormality detection point can be adjusted by adjusting the count value until the counter 6 overflows, and in the fastest case, the detection output can be generated at the point of 1 bit overflow of clock 1, which is different from the conventional timing signal. This is much faster than the monitoring method, which detects an abnormality after the time elapses to assemble one byte. Note that the frequency of the clock is set to timing signal 2.
The reason why the clock and timing signal are asynchronous is that the clock and timing signal are asynchronous, and as can be expected from the waveform diagram in Figure 3, a maximum of about 2 clocks are consumed at the end of timing signal 2 ( During this time, the counter is reset). When the counter 6 overflows, its output goes to the clock terminal of the wallip flop 7, and the input signal becomes "1".
Incorporate. Therefore, the Q output of this flip-flop 7 becomes "1", which becomes the abnormality detection flag 10. Further, this Q output passes through the OR gate 12 and becomes the character processing request flag 11, which interrupts the program to perform character processing (in this case, to read the abnormality detection flag 10). When the flag 10 is read as a result, an abnormality detection acceptance signal 8 is input to the flip-flop 7 and reset. A signal 9 is also input to the OR gate 12, which is a character processing request when the timing signal is normal. This timing signal abnormality detection circuit is used on the transmitting side in the case of full-duplex communication.
It is provided on each receiving side, but in the case of half-duplex communication, transmission and reception are performed at different times, so a multiplexer is provided in the input circuit of timing signal 2, and it is shared for abnormality detection of each timing signal for transmission and reception. can.

As is clear from the above explanation, according to the present invention, since no particular burden is placed on the program, the processing steps and processing time can be reduced, the amount of hardware can be reduced, and anomalies in timing signals can be avoided. It can be found immediately and provides detailed service.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of timing signals, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the operation. In the drawing, 3, 4, 5, and 6 are flip-flops, logic gates, and counters of an abnormality detection circuit, and 7 is a flip-flop for generating an interrupt signal. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A flip-flop and a logic gate that operate with a clock having a frequency four times or more higher than that of each transmitting or receiving element timing signal and that generates an output based on periodic changes in the timing signal, and that count the clock and are reset by the output, an abnormality detection circuit comprising a counter that overflows when the timing signal stops changing periodically; and an interrupt signal generation circuit that includes a flip-flop that is set by the overflow output of the counter and generates a program interrupt signal when receiving the output. An abnormality detection device in a synchronous communication control device, characterized by comprising: