KR100286536B1 - Arbitration apparatus of transrmission for multidrop communication system - Google Patents

Abstract

PURPOSE: A transmission arbitration apparatus of multidrop communication system is provided to stop the count of an arbitration clock counter until a synchronous clock is inputted, when a new board is mounted, thereby preventing from the data loss. CONSTITUTION: A node arbitration unit(10) includes a synchronous clock detecting unit(15) for detecting signal obtained from an arbitration unit. A counter(11) is controlled by the output signal of the synchronous clock detecting unit(15) and counts the bus arbitration signal(BAS) obtained from each node. A synchronous clock generating unit(12) generates a synchronous clock(ASS) in order to be synchronized the counter operation within a plurality of node units according to the counted value outputted from the counter(11). An arbitration clock generating unit(13) generates an arbitration clock(ACLK) for transmitting packet through the plurality of node units(20). An error detecting unit(14) detects the bus arbitration signal(BAS) generated from the node unit(20), thereby detecting an operating error.

Description

Arbitration apparatus of transrmission for multidrop communication system

The present invention relates to packet communication, and more particularly, in multidrop communication, when a plurality of nodes transmit, a clock counted from an arbitration circuit is counted at each node, and a value thereof corresponds to a slot number of the corresponding node. The present invention relates to a transmission arbitration apparatus of a multidrop communication system for transmitting data to be transmitted at the same time.

In general, in a conventional packet communication system, a plurality of nodes are connected to one router, and each of the nodes performs high level data link control (HDLC) communication with a lower processor.

1 is a schematic structural diagram of a conventional packet communication system for performing the above communication function.

As shown therein, a reception node unit 1 comprising a plurality of reception nodes (node 0-node m) each having a reception HDLC for converting reception serial packet data into parallel packet data and a reception first-in-first-out (Rx FIFO). And a router (2) for processing data obtained at each of the plurality of receiving nodes (node 0-node m), detecting a destination address of the data to be transmitted, and transmitting the transmission data to the corresponding destination, and the router (2). A first-in, first-out (Tx FIFO) and a transmission HDLC (Tx HDLC) for transmitting first-in, first-out, and serial data obtained from It consists of the transmission node part 3 which comprised.

The conventional packet communication system configured as described above converts HDLC packets coming from a lower processor into parallel packet data in a reception HDLC (Rx HDLC) in an arbitrary node (here, node 0) in the reception node unit 1 to receive first-in, first-out. It writes to the Rx FIFO and sends a signal to the router 2 to read it.

The router 2 then detects this in the internal detector and reads the data recorded in the RX FIFO. The address filter then extracts the destination address in the upper 4 bytes of the packet and determines which node to send to.

After that node is determined, it writes its transmission packet to a Tx FIFO in that node and signals it to read its data to the transmitting HDLC within that node.

Then, the transmission HDLC (Tx HDLC) in the node reads the parallel data recorded in the first-in, first-out, converts the serial data into serial data, and transmits the data to the corresponding destination.

However, such a conventional packet communication system sends an arbitration clock and a synchronous clock for counter operation to all nodes in the arbitration circuit, and each node operates the arbitration clock counter so that its slot number and count value match and there is data to transmit. In this case, it sends a bus arbitration signal indicating that it is time to transmit itself to each node and stops the operation of the intermediary clock counter until the transmission is completed.

At this time, if a new board is inserted while there is already communicating board, the arbitration clock counter of the newly inserted board starts counting from the beginning. This count value does not match the counter value of the board already installed. Therefore, the newly inserted card may randomly generate a bus arbitration signal.

As a result, a data collision occurs with a board that is communicating with one another, and the board that is communicating with one another loses data.

Accordingly, the present invention has been proposed to solve various problems occurring in the conventional packet communication system as described above.

According to the present invention, when a new board is mounted in a multidrop communication, the arbitration clock counter can not be counted until a synchronous clock is input, thereby preventing generation of a bus arbitration signal of the newly mounted board. The purpose of the present invention is to provide a transmission arbitration device of a multidrop communication system to prevent data loss of a board.

Apparatus according to the present invention for achieving the above object,

According to the synchronization clock obtained from the arbitration unit which arbitrates transmission of each node, it generates and transmits the mediation clock for packet transmission and the synchronization clock for counter operation and detects the status of the bus arbitration signal generated in each node. A node arbiter which arbitrates packet transmission of each node, and a node that counts an arbitration clock generated by the node arbiter and compares the count value with its slot ID and transmits packet data to be transmitted at a matching time point A self-router and a control unit comprising a unit;

And a CDMA digital channel card unit for arbitrating data transmission by driving the arbitration clock counter only by the synchronization clock obtained from the self-router and the controller.

In the above, the node arbiter in the self-router and the control unit includes a synchronization clock detection unit for detecting a synchronization clock obtained from the arbitration unit; A counter controlled by an output signal of the synchronous clock detector and counting a bus arbitration signal obtained at each node; A synchronization clock generator for generating a synchronization clock for synchronizing the counter operations in the plurality of node units according to the counter value output from the counter; An arbitration clock generator for generating an arbitration clock for transmitting the packet by the plurality of node units; And an error detection unit for detecting an operation error of the node unit by detecting a bus arbitration signal generated from the node unit.

The node unit in the self router and the control unit may further include: a counter for counting an arbitration clock obtained from the node arbitration unit; A comparator for comparing a counter value output from the counter with its slot ID; A latch unit operating in synchronization with the arbitration clock and holding its own transmission signal in accordance with a signal indicating the transmission request signal and its transmission time; A logic operation unit configured to perform a logic operation on its own transmission signal output from the latch unit and its own transmission time signal output from the comparison unit; And a flip-flop for generating a bus arbitration signal by synchronizing the signal output from the logic operation unit with the arbitration clock.

In the above, the logic operation unit is characterized in that it is composed of a logic summation element that logically sums its transmission signal output from the latch unit and its transmission time signal output from the comparison unit.

The CDMA digital channel card unit may include: a sync clock detector configured to sense a sync clock output from the self router and the controller; A counter controlled by a signal output from the synchronous clock detector and counting an arbitration clock obtained by the self router and the controller; A comparator for comparing a counter value output from the counter with its slot ID; A latch unit operating in synchronization with the arbitration clock and holding its own transmission signal in accordance with a signal indicating the transmission request signal and its transmission time; A logic operation unit configured to perform a logic operation on its own transmission signal output from the latch unit and its own transmission time signal output from the comparison unit; And a flip-flop for generating a bus arbitration signal by synchronizing the signal output from the logic operation unit with the arbitration clock.

1 is a schematic configuration diagram of a conventional packet communication system;

2 is a schematic structural diagram of a multidrop communication system to which the present invention is applied;

FIG. 3 is a detailed block diagram of the self router and controller SRCA-A1 of FIG. 2;

4 is a detailed block diagram of the CDMA digital channel card unit (CDCA-A1) shown in FIG.

<Explanation of symbols for main parts of drawing>

10: Node Arbitration Unit 11: Counter

12: Synchronous clock generator 13: Intermediate clock generator

14: error detection unit 15: synchronous clock detection unit

20: Node part 21: Counter

22: comparison 23: latch

24: logical operation unit 25: flip flop

31: Synchronous clock detector 32: Intermediate clock counter

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention.

2 is a schematic configuration diagram schematically showing the entire transmission arbitration apparatus of the multidrop communication system according to the present invention.

As shown in the figure, the base station interconnection network 4 and the address of the packet received from the base station interconnection network 4 are retrieved and delivered to their digital unit block, and then received and delivered to the corresponding node. If it is not a packet transmitted to its digital unit block, it blocks the function and transmits the packet transmitted from each node to the base station interconnection network 4 according to the synchronization clock obtained from the base station interconnection network 4. A transmission and reception monitoring unit 5 having a function, and an arbitration unit 6 for arbitrating transmission of a plurality of nodes, and a bus existing between the transmission and reception monitoring unit 5 and the arbitration unit 6; It consists of several node parts 7.

Here, each node in the plurality of node units 7 is used to receive a packet, and has an address filter, a counter, a counter value, and a filtering function for passing only its own address, broadcasting, and time of day (TOD) packet. Comparator for comparing slot numbers and HDLC.

In the multidrop communication system according to the present invention configured as described above, the arbitration unit 6 transmits the counter operation arbitration clock ACLK and the synchronization clock ASS to all nodes, and each node has an internal counter b. By comparing the slot number of the counter and the count value of the counter (b) and sending a bus arbitration signal (BAS) to each node indicating that it is the turn to transmit if there is transmission data. It stops the counter operation of other node until it stops.

The transmission arbitration apparatus of the multidrop communication system according to the present invention, which is an apparatus that actually implements the above-described concept of the present invention, is as shown in FIG.

As shown in the figure, a packet transmission arbitration clock ACLK and a counter operation synchronization clock ASS are generated according to a synchronization clock ASS obtained from the arbitration unit 6 which arbitrates transmission of each node. And a node arbitration unit 10 for detecting a state of a bus arbitration signal (BAS) generated at each node and arbitrating packet transmission of each node according to the result. A self-router and control unit SRCA-A1 comprising a node unit 20 for counting the arbitration clock ACLK, comparing the count value with its slot ID, and transmitting packet data to be transmitted at a matching time point; And a CDMA digital channel card unit (CDCA-A1) which arbitrates data transmission by driving the arbitration clock counter only by the synchronization clock obtained from the self-router and control unit SRCA-A1.

In the above, the node arbiter 10 in the self-router and control unit SRCA-A1 includes: a synchronous clock detector 15 for detecting a synchronous clock (ASS) obtained from the arbiter 6; A counter (11) for controlling driving by an output signal of the synchronous clock detector (15) and counting a bus arbitration signal (BAS) obtained at each node; A synchronization clock generator 12 generating a synchronization clock (ASS) for synchronizing the counter operations in the plurality of node units according to the counter value output from the counter (11); An arbitration clock generator (13) for generating an arbitration clock (ACLK) for the plurality of node units (20) to transmit packets; The error detection unit 14 detects an operation error of the node unit 20 by detecting a bus arbitration signal BAS generated from the node unit 20.

In addition, the node unit 20 includes: a counter 21 for counting an arbitration clock ACLK obtained from the node arbitration unit 10; A comparator 22 for comparing a counter value output from the counter 21 with its slot ID; A latch unit 23 which operates in synchronization with the arbitration clock and holds its transmission signal My-Tx according to a transmission request signal Tx-req and a signal My-turn indicating its transmission time; A logic operation unit (24) for performing a logic operation on its transmission signal output from the latch unit (23) and its transmission time signal output from the comparison unit (22); And a flip-flop 25 for generating a bus arbitration signal BAS by synchronizing the signal output from the logic operator 24 with the arbitration clock ACLK.

In this case, the logic operation unit 24 is composed of a logic sum element that logically combines its transmission signal output from the latch unit 23 and its transmission time signal output from the comparison unit 22 and outputs the resultant signal. .

In addition, the CDMA digital channel card unit CDCA-A1 may include: a sync clock detector 31 for detecting a sync clock ASS output from the self router and the controller SRCA-A1; An arbitration clock counter (32) for controlling driving by a signal output from the synchronization clock detector (31) and counting an arbitration clock (ACLK) obtained from the self router and the controller (SRCA-A1); A comparator 33 for comparing the counter value output from the arbitration clock counter 32 with its slot ID; A latch unit 34 operating in synchronization with the arbitration clock ACLK and holding its transmission signal in accordance with a transmission request signal and a signal indicating its transmission time; A logic operation unit (35) for performing a logic operation on its transmission signal output from the latch unit (34) and its transmission time signal output from the comparison unit (33); And a flip-flop 36 for generating a bus arbitration signal BAS by synchronizing the signal output from the logic operator 35 to the arbitration clock ACLK.

In the transmission arbitration apparatus of the multidrop communication system according to the present invention configured as described above, the arbitration unit 6 is performed by the synchronization clock detection unit 15 of the node arbitration unit 10 in the self-router and control unit SRCA-A1. It is detected whether or not the synchronization clock (ASS) is generated in this case, the counter 11 is operated when the synchronization clock (ASS) is detected. By the operation of the counter 11, the synchronous clock generator 12 generates a synchronous clock ASS so that all nodes are synchronized with this synchronous clock to operate the internal counter. In addition, the arbitration clock generator 13 generates an arbitration clock (ACLK) for all nodes to transmit a packet in synchronization with this clock, and delivers it to each node.

The node unit 20 having received the sync clock ASS and the arbitration clock ACLK counts the arbitration clock ACLK at the counter 21 and transfers the count value to the comparator 22.

Then, the comparator 22 compares the count value output from the counter 21 with its slot ID, and if it is the same, it is the turn that it transmits, and thus a signal (My-turn) indicating its transmission time. It is generated and delivered to the logic operation unit 24.

The logical operation unit 24 logically combines the My-turn signal and My-Tx, a signal indicating that there is a packet data to be transmitted from the latch unit 23, and transmits the result value to the flip-flop 25.

The flip-flop 25 then generates a bus arbitration signal BAS by synchronizing the signal with the arbitration clock ACLK.

In this case, the bus arbitration signal (BAS) is a signal in which all nodes float high whenever their slot number and count value are the same, and when the node transmits and there is a packet to transmit, the signal goes high until the end of packet transmission. It holds the counter operation of another node. When there is no packet to transmit, it floats high only during 1ACLK cycle.

That is, even if there is no packet to transmit, the bus arbitration signal BAS is output for one clock period of the arbitration clock ACLK, and the counter of each node continues to operate.

If there is a packet to be transmitted, the latch unit 23 maintains the My-Tx signal as a high signal so that the bus arbitration signal output from the flip-flop 25 is maintained.

This bus arbitration signal is sent to other nodes as well as its counter to hold the counter operation.

In addition, the bus arbitration signal (BAS) is maintained until the end of the packet transmission, and when the packet transmission ends, the Tx-req signal, which is a transmission request signal, goes low, and the bus arbitration signal (BAS) goes low to hold the counter. Retry operation, terminate the operation of own node and let the next node operate.

When the count value of the counter 21 is '0', the channel card CDCA-A1 of slot 0 transmits, and when the count reaches 10, SRCA-A1 finally transmits. It is necessary to return to CDCA-A1, so if the count value reaches 11, immediately output the synchronous clock (ASS) to reset the counter so that the count value starts from "0".

On the other hand, the error detection unit 14 in the node arbitration unit 10 should generate a bus arbitration signal (BAS) from the node. If the bus arbitration signal does not occur, an error occurs in the node corresponding to the count value. To the control unit (not shown) that controls the overall operation of the system with an interrupt (Error INT).

The long packet error is transmitted to the controller as an interrupt even when the bus arbitration signal BAS is maintained from one node longer than the time to transmit the longest packet length of 256 bytes.

Next, the CDMA digital channel card unit CDCA-A1, which is one node in each node unit, is a synchronization clock ASS generated by the self-router and control unit SRCA-A1 in the synchronization clock detection unit 31. If the synchronous clock is detected, the arbitration clock counter 32 is enabled to control the counting of the arbitration clock.

By doing so, when a new board (node) is mounted in a state where any node is communicating, the arbitration clock counter 32 does not immediately count, but counts the arbitration clock when the sync clock (ASS) is input. As a result, the board that is already communicating with the board is actually driven only when the communication is completed, so that the bus arbitration signal can be generated.

Therefore, even if a new board is newly installed while another board is communicating, the newly installed board does not generate a bus arbitration signal, and thus does not affect the board previously communicating. This prevents data loss on previously communicating boards.

On the other hand, the comparator 33 compares the count value output from the arbitration clock counter 32 with its slot ID (Slot-ID) and if it is the same, it is a signal indicating its transmission time because it is the turn of packet transmission (My- A turn is generated and transmitted to the logic operation unit 35.

The logical operation unit 35 logically combines the My-turn signal and My-Tx, a signal indicating that there is a packet data to be transmitted from the latch unit 34, and transmits the result value to the flip-flop 36.

Then, the flip-flop 36 generates a bus arbitration signal BAS by synchronizing the signal with the arbitration clock ACLK.

In this case, the bus arbitration signal (BAS) is a signal in which all nodes float high whenever their slot number and count value are the same, and when the node transmits and there is a packet to transmit, the signal goes high until the end of packet transmission. It holds the counter operation of other node and floats high only during 1ACLK cycle when there is no packet to transmit.

That is, even if there is no packet to transmit, the bus arbitration signal BAS is output for one clock period of the arbitration clock ACLK, and the counter of each node continues to operate.

If there is a packet to be transmitted, the latch unit 34 maintains the My-Tx signal as a high signal so that the bus arbitration signal output from the flip-flop 36 is maintained.

This bus arbitration signal is sent to other nodes as well as its counter to hold the counter operation.

In addition, the bus arbitration signal (BAS) is maintained until the end of the packet transmission, and when the packet transmission ends, the Tx-req signal, which is a transmission request signal, goes low, and the bus arbitration signal (BAS) goes low to hold the counter. Retry operation, terminate the operation of own node and let the next node operate.

When the arbitration clock counter 32 has a count value of '0', the channel card (CDCA-A1) of slot 0 is to be transmitted, and when it is 10, SRCA-A1 is finally to be transmitted. "Because we have to go back to the CDCA-A1 of the slot, when the count value reaches 11, we output the synchronous clock (ASS) and reset the counter so that the count value starts from" 0 ".

As described above, the present invention drives the internal arbitration clock counter at the time of detecting the synchronization signal generated by the arbitration unit during packet communication, so that a new board is mounted while the existing board is communicating. Even if the bus arbitration signal is suppressed, data collision can be prevented in advance.

Claims (3)

In a multidrop communication system, A synchronous clock detector for sensing a synchronous clock obtained from an arbitration unit that arbitrates transmission of each node, a first counter controlled by an output signal of the synchronous clock detector and counting a bus arbitration signal obtained at each node; A synchronization clock generator for generating a synchronous clock such that counter operations in the plurality of node units are synchronized according to a counter value output from the first counter, and an arbitration clock generator for generating an arbitration clock for causing the plurality of node units to transmit packets An error detection unit for detecting an operation error of the node unit by detecting a bus arbitration signal generated from the node unit, a second counter for counting the arbitration clock obtained in the arbitration clock generating unit, and a count output from the second counter; A comparison unit for comparing a value with its slot ID, and operating in synchronization with the arbitration clock, A latch unit for latching its own transmission signal according to a signal and a signal indicating its own transmission time, and a logic operation unit for logically computing its own transmission time signal output from the latching unit and its own transmission time signal output from the comparison unit A self-router and a controller configured to generate a bus arbitration signal by synchronizing the signal output from the logic operation unit with the arbitration clock; A synchronization clock detection unit for detecting a synchronization clock output from the self router and the controller, a drive controlled by a signal output from the synchronization clock detection unit, and a counter for counting an arbitration clock obtained from the self router and the control unit; A latch for comparing the counter value output from the counter with its slot ID and a latch for latching its own transmission signal according to a signal indicating that the transmission request signal and its transmission time are synchronized with the arbitration clock. And a logic operation unit for performing a logic operation on its own transmission signal output from the latch unit and its transmission time signal output from the comparison unit, and a bus arbitration signal by synchronizing the signal output from the logic operation unit with the arbitration clock. Characterized in that it comprises a CDMA digital channel card portion consisting of flip-flops for generating a Transmission arbitration apparatus of a multidrop communication system. The logic operation unit of claim 1, wherein the logic operation unit in the self router and the control unit comprises: A multidrop comprising: a logical summation element that logically combines its own transmission signal output from the latch unit of the self router and the control unit with its own transmission time signal output from the comparison unit of the self router and the control unit. Transmission arbitration apparatus in a communication system. The logical operation unit in the CDMA digital channel card unit comprises: A multidrop comprising a logical sum element which logically combines its own transmission signal output from the latch section of the CDMA digital channel card section and its own transmission time signal output from the comparator section of the CDMA digital channel card section. Transmission arbitration apparatus in a communication system.