JPS6450132A - Watch dog timer - Google Patents

Watch dog timer

Info

Publication number
JPS6450132A
JPS6450132A JP62206658A JP20665887A JPS6450132A JP S6450132 A JPS6450132 A JP S6450132A JP 62206658 A JP62206658 A JP 62206658A JP 20665887 A JP20665887 A JP 20665887A JP S6450132 A JPS6450132 A JP S6450132A
Authority
JP
Japan
Prior art keywords
signal
inputted
output
watch dog
dog timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62206658A
Other languages
Japanese (ja)
Inventor
Takashi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62206658A priority Critical patent/JPS6450132A/en
Publication of JPS6450132A publication Critical patent/JPS6450132A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To suppress the increase of the hardware quantity, and to prevent the increase of a fault rate by monitoring plural information processors by one watch dog timer. CONSTITUTION:As for synchronizing signals 10, 11 generated from information processors 1, 2, its synchronizing state is deteriorated, when a fault is generated, and a watch dog timer 3 detects a faulty state thereby. FFs 301, 302 are set, when the signals 10, 11 are inputted to the respective terminals S, and an output is held in H. When a reset signal is inputted to the respective terminals R, said FFs are reset, and the output is held in L. When the reset signal 12 is inputted, a counter 303 is initialized, and starts time counting again. When the time counting value becomes higher than a prescribed value, the counter 303 sends out an overflow signal 13. When the signal 13 is inputted, and the output of the FF 301 is L, an AND circuit 305 sends out an abnormal signal 15, and when the signal 13 is inputted, and the output of the FF 302 is L, an AND circuit 306 sends out an abnormal signal 16.
JP62206658A 1987-08-20 1987-08-20 Watch dog timer Pending JPS6450132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62206658A JPS6450132A (en) 1987-08-20 1987-08-20 Watch dog timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62206658A JPS6450132A (en) 1987-08-20 1987-08-20 Watch dog timer

Publications (1)

Publication Number Publication Date
JPS6450132A true JPS6450132A (en) 1989-02-27

Family

ID=16526995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62206658A Pending JPS6450132A (en) 1987-08-20 1987-08-20 Watch dog timer

Country Status (1)

Country Link
JP (1) JPS6450132A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112018000271B4 (en) 2017-01-20 2021-12-09 Panasonic Intellectual Property Management Co., Ltd. Imaging device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112018000271B4 (en) 2017-01-20 2021-12-09 Panasonic Intellectual Property Management Co., Ltd. Imaging device

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