JPS56157517A - Detecting system for input clock fault - Google Patents

Abstract

PURPOSE:To protect a device from faults, by providing a counter, which counts high-speed clocks and is initialized when a low-speed clock sppears, and a counter which is initialized when count contents coincide with the frequency ratio of the high-speed clock to the low-speed clock. CONSTITUTION:When the input clock stops, a counter 512 starts counting; and if this state continues for approximately >=3 frames, the count value of the counter reaches a prescribed value, and as a result, the output of the decoder becomes high- level to set an FF82. This setting of the FF82 is regarded as the fixed fault of input clock break to request the route switching to the clock route switching control circuit. A counter 91 monitors the frequency ratio of the reference clock to the frame clock by the cooperative action of a counter 75 and a decoder 76. If this frequency ratio is erroneous three times continuously, the FF82 is set to issue the clock route switching request. As a result, the device is protected from not only simple clock break but also intermittent faults generated momently.