JPS5773418A - Watchdog timer - Google Patents
Watchdog timerInfo
- Publication number
- JPS5773418A JPS5773418A JP55150438A JP15043880A JPS5773418A JP S5773418 A JPS5773418 A JP S5773418A JP 55150438 A JP55150438 A JP 55150438A JP 15043880 A JP15043880 A JP 15043880A JP S5773418 A JPS5773418 A JP S5773418A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- time
- counter
- output
- cpu3
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To obtain a watchdog timer which is capable of the time-out of time even through the clock pulse is discontinued, by providing an oscillating circuit that produces the clock pulse plus an FF that detects the fault of a CPU and dilivers the time-out signal. CONSTITUTION:An oscillating circuit 1 produces a clock pulse of a certain frequency to deliver it to a CPU3, a counter 2 and a triggerable 1-shot circuit 10, respectively. When the circuit 1 is working in a normal state, the circuit 10 is kept in a metastable state. Then the outputs of the counter 2 and the circuit 10 are supplied to an FF4, and the output of the FF4 is stable at 0. In case the circuit 1 has a fault, the output of the FF4 is inverted to 1 from 0 since no output of the circuit 10 exists. And the CPU3 counts out the time. At the same time, the counter 2 continues its counting up to a prescribed value as long as the CPU3 does not deliver the clear signal to the counter 2. Thus a carry-out signal is sent to the FF4, and the output of the FF4 is inverted to 1 from 0 to count out the time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55150438A JPS5773418A (en) | 1980-10-27 | 1980-10-27 | Watchdog timer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55150438A JPS5773418A (en) | 1980-10-27 | 1980-10-27 | Watchdog timer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5773418A true JPS5773418A (en) | 1982-05-08 |
Family
ID=15496926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55150438A Pending JPS5773418A (en) | 1980-10-27 | 1980-10-27 | Watchdog timer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5773418A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS534823B2 (en) * | 1974-09-30 | 1978-02-21 | ||
| JPS54103647A (en) * | 1978-02-01 | 1979-08-15 | Nec Corp | Program process monitor system |
-
1980
- 1980-10-27 JP JP55150438A patent/JPS5773418A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS534823B2 (en) * | 1974-09-30 | 1978-02-21 | ||
| JPS54103647A (en) * | 1978-02-01 | 1979-08-15 | Nec Corp | Program process monitor system |
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