JPS5612124A - External signal off delay timer unit - Google Patents

External signal off delay timer unit

Info

Publication number
JPS5612124A
JPS5612124A JP8848179A JP8848179A JPS5612124A JP S5612124 A JPS5612124 A JP S5612124A JP 8848179 A JP8848179 A JP 8848179A JP 8848179 A JP8848179 A JP 8848179A JP S5612124 A JPS5612124 A JP S5612124A
Authority
JP
Japan
Prior art keywords
output
reset
signal
counting
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8848179A
Other languages
Japanese (ja)
Inventor
Aritaka Yorifuji
Kenichi Yoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP8848179A priority Critical patent/JPS5612124A/en
Publication of JPS5612124A publication Critical patent/JPS5612124A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals

Abstract

PURPOSE:To prevent an off-delay timer from malfunctioning in application of electric power, by resetting a counting part the output of logical operation between an external signal and the output of a flip-flop circuit reset in the application of electric power. CONSTITUTION:On feed (a) of electric power, FF5 is reset and output Q' becomes ''1'' and is supplied to reset part 4 through exclusive OR circuit 6 to let reset part 4 generate an output, resetting counting part 2. Once external signal SP is input, FF5 is set and output Q becomes ''1'', but circuit 6 outputs signal SP and while counting part 2 stays reset, output ''1'' is passed through output part 3' to generate output signal (c) of the timer. As signal SP disappears, the signal from circuit 6 becomes ''0'', and consequently counting part 2 starts counting the output of oscillation part 1 and, when reaching a preset count value, generates its output to reset FF5, making the delay output from output part 3' into ''0''.
JP8848179A 1979-07-12 1979-07-12 External signal off delay timer unit Pending JPS5612124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8848179A JPS5612124A (en) 1979-07-12 1979-07-12 External signal off delay timer unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8848179A JPS5612124A (en) 1979-07-12 1979-07-12 External signal off delay timer unit

Publications (1)

Publication Number Publication Date
JPS5612124A true JPS5612124A (en) 1981-02-06

Family

ID=13943978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8848179A Pending JPS5612124A (en) 1979-07-12 1979-07-12 External signal off delay timer unit

Country Status (1)

Country Link
JP (1) JPS5612124A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6176730U (en) * 1984-10-26 1986-05-23
JPS63104128U (en) * 1986-12-25 1988-07-06
JPS63176731U (en) * 1986-12-25 1988-11-16

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6176730U (en) * 1984-10-26 1986-05-23
JPS63104128U (en) * 1986-12-25 1988-07-06
JPS63176731U (en) * 1986-12-25 1988-11-16

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