JPS6436217A - Asynchronizing n-adic counter - Google Patents

Asynchronizing n-adic counter

Info

Publication number
JPS6436217A
JPS6436217A JP19173987A JP19173987A JPS6436217A JP S6436217 A JPS6436217 A JP S6436217A JP 19173987 A JP19173987 A JP 19173987A JP 19173987 A JP19173987 A JP 19173987A JP S6436217 A JPS6436217 A JP S6436217A
Authority
JP
Japan
Prior art keywords
pulse
clock signal
reset
decode
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19173987A
Other languages
Japanese (ja)
Inventor
Koichiro Tsujino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP19173987A priority Critical patent/JPS6436217A/en
Publication of JPS6436217A publication Critical patent/JPS6436217A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To ensure the resetting by outputting a decode pulse when the count reaches N-1 and using a 2nd clock signal having a frequency being an integral multiple of the frequency of a 1st clock signal for count-up so as to apply differentiation to a decode pulse synchronizingly and forming a reset pulse. CONSTITUTION:When the count by an output of affirmative output terminals Q1-Q3 of T flip-flops 1-3 reaches '5' in an asynchronizing, e.g., 6-adic counter, a decode pulse PD is outputted from an AND circuit 4. The decode pulse PD is subject to synchronizing differentiation by using the 2nd clock signal phiB and a reset pulse PR is outputted from an AND circuit 7. The period of the clock signal phiB is longer than the minimum pulse width required for the reset operation and set shorter than the setup time for counting up the succeeding value. Thus, the minimum width of the reset pulse PR is guaranteed and the reset is ensured. Moreover, no hindrance is given to countup.
JP19173987A 1987-07-31 1987-07-31 Asynchronizing n-adic counter Pending JPS6436217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19173987A JPS6436217A (en) 1987-07-31 1987-07-31 Asynchronizing n-adic counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19173987A JPS6436217A (en) 1987-07-31 1987-07-31 Asynchronizing n-adic counter

Publications (1)

Publication Number Publication Date
JPS6436217A true JPS6436217A (en) 1989-02-07

Family

ID=16279694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19173987A Pending JPS6436217A (en) 1987-07-31 1987-07-31 Asynchronizing n-adic counter

Country Status (1)

Country Link
JP (1) JPS6436217A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110974766A (en) * 2020-02-14 2020-04-10 广州巴宝莉化妆品有限公司 Rose fragrance body lotion and preparation process thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110974766A (en) * 2020-02-14 2020-04-10 广州巴宝莉化妆品有限公司 Rose fragrance body lotion and preparation process thereof

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