JPS5799818A - Noise pulse eliminating circuit - Google Patents

Noise pulse eliminating circuit

Info

Publication number
JPS5799818A
JPS5799818A JP55176858A JP17685880A JPS5799818A JP S5799818 A JPS5799818 A JP S5799818A JP 55176858 A JP55176858 A JP 55176858A JP 17685880 A JP17685880 A JP 17685880A JP S5799818 A JPS5799818 A JP S5799818A
Authority
JP
Japan
Prior art keywords
counter
inputted
noise pulse
noise
active state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55176858A
Other languages
Japanese (ja)
Inventor
Kazuo Suzuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP55176858A priority Critical patent/JPS5799818A/en
Publication of JPS5799818A publication Critical patent/JPS5799818A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To eliminate surely single or repeatedly inputted noise pulses, by connecting two coutners successively and by making the operation time of the counter of the succeeding stage longer than that of the counter of the preceding stage. CONSTITUTION:Counters 21 and 22 are quad and octal counters respectively. When a noise pulse of the positive polarity which has the duration shorter than the period of a clock signal is inputted to a terminal (a), the counter 21 is changed to the active state, but the counter 21 is reset before completion of the counting operation not to change the state of an output terminal 212. When a noise pulse of the negative polarity is inputted, the counter 21 is reset, but the counter 22 becomes the active state. When the noise pulse is terminated, the counter 21 becomes the active state to start counting the clock signal, but the counter 21 is reset before the counter 22 completes counting, and therefore, the state of an output terminal (c) is not changed. Even if noise pulses are inputted repeatedly, the counter 22 is not influenced.
JP55176858A 1980-12-15 1980-12-15 Noise pulse eliminating circuit Pending JPS5799818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55176858A JPS5799818A (en) 1980-12-15 1980-12-15 Noise pulse eliminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55176858A JPS5799818A (en) 1980-12-15 1980-12-15 Noise pulse eliminating circuit

Publications (1)

Publication Number Publication Date
JPS5799818A true JPS5799818A (en) 1982-06-21

Family

ID=16021048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55176858A Pending JPS5799818A (en) 1980-12-15 1980-12-15 Noise pulse eliminating circuit

Country Status (1)

Country Link
JP (1) JPS5799818A (en)

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