JPS648725A - Counter reset circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a peripheral circuit for counter reset by adopting the constitution such that an internal clock signal subject to frequency division is utilized as a pulse for counter reset. CONSTITUTION:An external clock signal passes through a selector 5 and synchronized with an internal clock signal by a synchronizing circuit 4 and the result is given to a counter 1. The counter 1 is reset by switching the output of the selector 5 into the internal clock signal subject to frequency division for a prescribed period by a frequency division circuit 2 from the external clock signal. In receiving the internal clock signal frequency-divided, the counter 1 gives an interruption request to control the selector 5 so as to switch the signal from the internal clock signal to the external clock signal. Thus, the parallel I/O port is used for other signal processing and no peripheral circuit for reset is required, thus cost is reduced.