JPS5616925A - Control system for clock switching - Google Patents

Control system for clock switching

Info

Publication number
JPS5616925A
JPS5616925A JP9091879A JP9091879A JPS5616925A JP S5616925 A JPS5616925 A JP S5616925A JP 9091879 A JP9091879 A JP 9091879A JP 9091879 A JP9091879 A JP 9091879A JP S5616925 A JPS5616925 A JP S5616925A
Authority
JP
Japan
Prior art keywords
clock
pulse
defective
change
over command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9091879A
Other languages
Japanese (ja)
Inventor
Hiroyuki Mase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9091879A priority Critical patent/JPS5616925A/en
Publication of JPS5616925A publication Critical patent/JPS5616925A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the defective pulses from being generated, by synchronizing the frequency divided clock of opposite phase switched and selected based on the change-over command signal to the clock before division.
CONSTITUTION: The clock (a) becomes the clocks (b),(c) of opposite phase frequency-divided into 1/2 or the like by the JK type FFs 1,2, and fed to the NAND gates 4,5, to which the Q,Q' outputs produced by the JK type FF3 are respectively fed in response to the change-over command pulse (d) of high and low level. Thus, the defective synchronizing pulse 2X different from the synchronism of the clocks (b),(c) is included to the clock (c) etc. switched from the clock (b) etc. of the output (e) from the OR gate 6. When this pulse (e) is processed for synchronism at the JK FF8 taking the clock (a) before the frequency division, it becomes the clock (f) without pulse X before and after the switching, allowing to prevent the production of defective pulse and to be the control pulse without malfunction. Further, the change-over command signal is synchronized with the clock before frequency division to obtain the same state.
COPYRIGHT: (C)1981,JPO&Japio
JP9091879A 1979-07-19 1979-07-19 Control system for clock switching Pending JPS5616925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9091879A JPS5616925A (en) 1979-07-19 1979-07-19 Control system for clock switching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9091879A JPS5616925A (en) 1979-07-19 1979-07-19 Control system for clock switching

Publications (1)

Publication Number Publication Date
JPS5616925A true JPS5616925A (en) 1981-02-18

Family

ID=14011796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9091879A Pending JPS5616925A (en) 1979-07-19 1979-07-19 Control system for clock switching

Country Status (1)

Country Link
JP (1) JPS5616925A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738398A (en) * 1993-07-15 1995-02-07 Nec Corp Clock switching circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54112606A (en) * 1978-02-22 1979-09-03 Teac Corp Device for converting dm signal to nrz signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54112606A (en) * 1978-02-22 1979-09-03 Teac Corp Device for converting dm signal to nrz signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738398A (en) * 1993-07-15 1995-02-07 Nec Corp Clock switching circuit

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