JPS6416121A - Digital pll circuit - Google Patents

Digital pll circuit

Info

Publication number
JPS6416121A
JPS6416121A JP62173274A JP17327487A JPS6416121A JP S6416121 A JPS6416121 A JP S6416121A JP 62173274 A JP62173274 A JP 62173274A JP 17327487 A JP17327487 A JP 17327487A JP S6416121 A JPS6416121 A JP S6416121A
Authority
JP
Japan
Prior art keywords
signal
ring counter
circuit
time
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62173274A
Other languages
Japanese (ja)
Inventor
Atsushi Niino
Keiji Ueki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP62173274A priority Critical patent/JPS6416121A/en
Publication of JPS6416121A publication Critical patent/JPS6416121A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To simplify the circuit constitution by circulating signal '1' in a ring counter by a clock signal to lead out the output signal from a specific stage of the ring counter. CONSTITUTION:A ring counter 10 consists of FFs 1-5 and gates G1-G11. When an input signal fi is not supplied, the ring counter 10 is operated synchronously with a clock signal CLK and signal '1' is circulated in FFs 1-5. At this time, signal '1' is circulated through Q1, G2-G11, and D1. A lock detecting circuit 20 consists of a gate G14 and a counter 21 : and when the simultaneous occurrence of pulse '1' of an output signal f0 and that of the input signal fi continues for three pulses, the circuit 20 decides phase lock, and a lock detection signal at this time goes to '0'. The signal Q is '1' before this time. Signal '1' is skipped and transmitted or is returned to the preceding stage in accordance with the timing comparison between the position of signal '1' in the ring counter and the signal fi, thereby allowing the phase of the signal f0 to follow up the signal fi.
JP62173274A 1987-07-10 1987-07-10 Digital pll circuit Pending JPS6416121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62173274A JPS6416121A (en) 1987-07-10 1987-07-10 Digital pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62173274A JPS6416121A (en) 1987-07-10 1987-07-10 Digital pll circuit

Publications (1)

Publication Number Publication Date
JPS6416121A true JPS6416121A (en) 1989-01-19

Family

ID=15957408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62173274A Pending JPS6416121A (en) 1987-07-10 1987-07-10 Digital pll circuit

Country Status (1)

Country Link
JP (1) JPS6416121A (en)

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