JPS6481527A - Phase comparator - Google Patents

Phase comparator

Info

Publication number
JPS6481527A
JPS6481527A JP62239408A JP23940887A JPS6481527A JP S6481527 A JPS6481527 A JP S6481527A JP 62239408 A JP62239408 A JP 62239408A JP 23940887 A JP23940887 A JP 23940887A JP S6481527 A JPS6481527 A JP S6481527A
Authority
JP
Japan
Prior art keywords
flop
flip
edge
clock
gate signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62239408A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP62239408A priority Critical patent/JPS6481527A/en
Publication of JPS6481527A publication Critical patent/JPS6481527A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To make the phase comparison output characteristic symmetrical independently of the pulse width of an input signal by accepting only the leading of a data signal for a period of a gate signal representing the phase comparison enable range. CONSTITUTION:A gate signal generating section 9 generates a gate signal existing for a period corresponding to the period of the clock from the production of one edge of the clock CK. A 1st flip-flop 10 reaches one state at one edge of an edge data input (b) in the presence of the gate signal. The output of the flip-flop 10 is stored by a 2nd flip-flop 3 acted at one edge of the said clock CK. When a 2nd flip-flop 3 reaches one state, the 1st flip-flop 10 is brought into the other state to output the output of the 1st flip-flop as a signal corresponding to the phase difference information between the edge input (b) and the clock CK.
JP62239408A 1987-09-24 1987-09-24 Phase comparator Pending JPS6481527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62239408A JPS6481527A (en) 1987-09-24 1987-09-24 Phase comparator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62239408A JPS6481527A (en) 1987-09-24 1987-09-24 Phase comparator

Publications (1)

Publication Number Publication Date
JPS6481527A true JPS6481527A (en) 1989-03-27

Family

ID=17044328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62239408A Pending JPS6481527A (en) 1987-09-24 1987-09-24 Phase comparator

Country Status (1)

Country Link
JP (1) JPS6481527A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8164994B2 (en) 2005-06-27 2012-04-24 Samsung Electonics Co., Ltd. Apparatus for generating tracking signal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223225A (en) * 1984-04-18 1985-11-07 Matsushita Electric Ind Co Ltd Phase locked loop

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223225A (en) * 1984-04-18 1985-11-07 Matsushita Electric Ind Co Ltd Phase locked loop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8164994B2 (en) 2005-06-27 2012-04-24 Samsung Electonics Co., Ltd. Apparatus for generating tracking signal

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