JPS55110456A - Modulation method for digital signal and its modulation circuit - Google Patents
Modulation method for digital signal and its modulation circuitInfo
- Publication number
- JPS55110456A JPS55110456A JP1871479A JP1871479A JPS55110456A JP S55110456 A JPS55110456 A JP S55110456A JP 1871479 A JP1871479 A JP 1871479A JP 1871479 A JP1871479 A JP 1871479A JP S55110456 A JPS55110456 A JP S55110456A
- Authority
- JP
- Japan
- Prior art keywords
- output
- fed
- circuit
- input
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE: To make easy for bit synchronism and to enable to include all the information at the front edge of pulses, by zeroing the average value of a pair of positive and negative pulses every period and reducing the low frequency component including DC component.
CONSTITUTION: The data (a) of the data input terminal 11 and the first clock signal (b) are fed to D type FF 15, the output data (e) is fed to the three input NAND circuit 17, and the second clock signal (c) and the inversion signal (f) of the data (a) are fed to the circuit 17. The output (g) of the circuit 17 and the output (h) of the first two input NAND circuit 18 are taken for logic with the second two input NAND circuit 20, and the output is fed to JKFF 21. Further, the output (i) taking the logic for the signals (b) and (c) at the two input NOR circuit 19 is fed to FF21, the output of FF21 is fed to 8 or 6-bit shift register 22, the third clock signal (d) is fed to the register 22 to output the modulation signal having equal time interval at the output terminal 26 via the first, second 4 or 3-bit comparators 23, 24 and three input OR circuit 25.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1871479A JPS55110456A (en) | 1979-02-20 | 1979-02-20 | Modulation method for digital signal and its modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1871479A JPS55110456A (en) | 1979-02-20 | 1979-02-20 | Modulation method for digital signal and its modulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55110456A true JPS55110456A (en) | 1980-08-25 |
| JPS6243268B2 JPS6243268B2 (en) | 1987-09-12 |
Family
ID=11979318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1871479A Granted JPS55110456A (en) | 1979-02-20 | 1979-02-20 | Modulation method for digital signal and its modulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55110456A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59113514A (en) * | 1982-12-20 | 1984-06-30 | Matsushita Electric Ind Co Ltd | Recording and reproducing method of binary information |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63144309U (en) * | 1987-03-16 | 1988-09-22 |
-
1979
- 1979-02-20 JP JP1871479A patent/JPS55110456A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59113514A (en) * | 1982-12-20 | 1984-06-30 | Matsushita Electric Ind Co Ltd | Recording and reproducing method of binary information |
| JPH0526272B2 (en) * | 1982-12-20 | 1993-04-15 | Matsushita Electric Ind Co Ltd |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6243268B2 (en) | 1987-09-12 |
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