JPS5516556A - Time readjustment system for data signal - Google Patents

Time readjustment system for data signal

Info

Publication number
JPS5516556A
JPS5516556A JP8924178A JP8924178A JPS5516556A JP S5516556 A JPS5516556 A JP S5516556A JP 8924178 A JP8924178 A JP 8924178A JP 8924178 A JP8924178 A JP 8924178A JP S5516556 A JPS5516556 A JP S5516556A
Authority
JP
Japan
Prior art keywords
data signal
delay
output
pulse
modulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8924178A
Other languages
Japanese (ja)
Other versions
JPS581589B2 (en
Inventor
Shiyunichi Iizukuri
Nobuhiko Onda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53089241A priority Critical patent/JPS581589B2/en
Publication of JPS5516556A publication Critical patent/JPS5516556A/en
Publication of JPS581589B2 publication Critical patent/JPS581589B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To make adjustment making use of AND between a modulating clock pulse and a singal obtained by inverting the delay of a modulated data signal by the delay of a data signal.
CONSTITUTION: Dara signal I(B) lagging by td and modulating pulse II(A) are both applied to NAND circuit 4. Here, the output is narrow in pulse width due to delay as shown by (V). The output of NAND circuit 6 supplied with modulating pulse III(C) and an inverted data signal is shown by (VI). Final output (VII) shows the correct output of the modulated data. In this way, the distortion and delay of the modulated data due to the delay of the data signal can be adjusted by a simple circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP53089241A 1978-07-21 1978-07-21 Data signal time regulation method Expired JPS581589B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53089241A JPS581589B2 (en) 1978-07-21 1978-07-21 Data signal time regulation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53089241A JPS581589B2 (en) 1978-07-21 1978-07-21 Data signal time regulation method

Publications (2)

Publication Number Publication Date
JPS5516556A true JPS5516556A (en) 1980-02-05
JPS581589B2 JPS581589B2 (en) 1983-01-12

Family

ID=13965240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53089241A Expired JPS581589B2 (en) 1978-07-21 1978-07-21 Data signal time regulation method

Country Status (1)

Country Link
JP (1) JPS581589B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6116710A (en) * 1991-01-18 2000-09-12 Canon Kabushiki Kaisha Ink jet recording method and apparatus using thermal energy

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6116710A (en) * 1991-01-18 2000-09-12 Canon Kabushiki Kaisha Ink jet recording method and apparatus using thermal energy

Also Published As

Publication number Publication date
JPS581589B2 (en) 1983-01-12

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