JPS56161738A - Synchronizing clock generating system - Google Patents

Synchronizing clock generating system

Info

Publication number
JPS56161738A
JPS56161738A JP6530780A JP6530780A JPS56161738A JP S56161738 A JPS56161738 A JP S56161738A JP 6530780 A JP6530780 A JP 6530780A JP 6530780 A JP6530780 A JP 6530780A JP S56161738 A JPS56161738 A JP S56161738A
Authority
JP
Japan
Prior art keywords
counter
synchronizing clock
correction data
calculating section
reception data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6530780A
Other languages
Japanese (ja)
Inventor
Seishi Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6530780A priority Critical patent/JPS56161738A/en
Publication of JPS56161738A publication Critical patent/JPS56161738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To avoid the disturbance in synchronism even to noise, by providing a specific synchronizing clock counter, a correction data calculating section and a gate means, and obtaining the synchronizing clock signal from the specific bit of the said counter. CONSTITUTION:A synchronizing clock counter 1 which counts up N times, e.g., 16 times the basic clock (k) of a reception data a3, and a correction data calculating section 7 which sets the correction value of the counter 1 through the use of the output state of the counter 1 at the rise of the reception data a3, are provided. Further, gate means 10, 11 which inputs the said correction data P0-P3 to the counter 1 by using the output of an inhibit flag 6 reset with the fall of the carry signal outputted from the counter 1, and set with the fall of the reception data a3, are provided. Further, the synchronizing clock signal CK is obtained from the specific bit of a counter (e.g., C3). The correction data calculating section 7 consists of a register 8 and an adjust gate 9 making logical operation as shown in Figure, for example.
JP6530780A 1980-05-19 1980-05-19 Synchronizing clock generating system Pending JPS56161738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6530780A JPS56161738A (en) 1980-05-19 1980-05-19 Synchronizing clock generating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6530780A JPS56161738A (en) 1980-05-19 1980-05-19 Synchronizing clock generating system

Publications (1)

Publication Number Publication Date
JPS56161738A true JPS56161738A (en) 1981-12-12

Family

ID=13283114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6530780A Pending JPS56161738A (en) 1980-05-19 1980-05-19 Synchronizing clock generating system

Country Status (1)

Country Link
JP (1) JPS56161738A (en)

Similar Documents

Publication Publication Date Title
JPS53148317A (en) Error correction unit for time axis
JPS53149076A (en) Digital frequency detecting circuit
JPS53144621A (en) Video signal processing system
JPS5218363A (en) Circuitry for clock
JPS56161738A (en) Synchronizing clock generating system
JPS57197961A (en) Conversion system for image data
JPS5362908A (en) Bit clock reproducer
JPS52108179A (en) Electronic watch
JPS5381059A (en) Digital phase synchronizing system
JPS553265A (en) Reception timing device for digital code
JPS5665316A (en) Processor for digital signal
JPS5286758A (en) High accurate digital delay circuit
JPS5448473A (en) Coder
JPS5243466A (en) Electronic watch
JPS52113146A (en) Synchronous system
JPS5321511A (en) Digital signal processing system
JPS5419346A (en) Digital phase synchronous system
JPS5414145A (en) Polygonal line decoder of digital type
JPS5425643A (en) Data channel clear system
JPS52140246A (en) Information processing unit
JPS5227667A (en) Digital indicating timepiece of all electronic type
JPS5663625A (en) Timer circuit
JPS57140054A (en) Ami coding circuit
JPS53135594A (en) Cursor display unit
JPS5379437A (en) Key signal read-in system