JPS5719822A - Information processor - Google Patents

Abstract

PURPOSE:To make an external waiting signal generating circuit unnecessary, by providing an FF for generating a control signal when a count value of a counting circuit which synchronizes with read/write signals and counts an internal clock has coincided with a stored value. CONSTITUTION:A read signal 118 or a write signal 119 from a timing controlling circuit 101 for controlling a processing cycle of a CPU is inputted to a NAND gate 107, an inverter 117 and an FF108 through a NAND gate 106 of a pulse generating circuit 103. To the gate 107 is inputted an internal clock 123 of the CPU, and outputs of the gate 107 and the inverter 111 are inputted to a binary down-counter 105. The counter 105 counts the clock 123 by synchronizing with a read or write signal, outputs a borrow signal 124 when its count value coincides with a value which has been stored in a latching circuit 104, and outputs a wait control signal to the outside from a terminal 115 through the FF108. The circuit 101 is made a stop state by a wait controlling circuit 102 until the signal 124 is outputted after the signal 118 or 119 has been outputted.