JPS5453956A - Timing logic circuit - Google Patents

Timing logic circuit

Info

Publication number
JPS5453956A
JPS5453956A JP12009977A JP12009977A JPS5453956A JP S5453956 A JPS5453956 A JP S5453956A JP 12009977 A JP12009977 A JP 12009977A JP 12009977 A JP12009977 A JP 12009977A JP S5453956 A JPS5453956 A JP S5453956A
Authority
JP
Japan
Prior art keywords
high level
misfet
pulse signal
output
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12009977A
Other languages
Japanese (ja)
Inventor
Takashi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12009977A priority Critical patent/JPS5453956A/en
Publication of JPS5453956A publication Critical patent/JPS5453956A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE: To establish the logical output signal giving the level element of the input pulse to the timing element, by providing the delivery gate MISFET controlled with the output of the inverter circuit.
CONSTITUTION: When the pulse signal ϕ2 is made to high level at a slow time, since the pulse signal ϕ10 is at high level earlier, high level state is made to the gate of the driving MISFET Q2 of one inverter circuit, and MISFET Q3 is turned on and the delivery gate MISFET Q6 is turned off. Accordingly, even if the pulse signal ϕ2 is changed to high level later, but the driving MISFET Q1 in another inverter circuit can not be turned on and OFF state is maintained. Thus, the output pulse ϕ3 is obtained for the high level output rising with the leading of the pulse signal ϕ10
COPYRIGHT: (C)1979,JPO&Japio
JP12009977A 1977-10-07 1977-10-07 Timing logic circuit Pending JPS5453956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12009977A JPS5453956A (en) 1977-10-07 1977-10-07 Timing logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12009977A JPS5453956A (en) 1977-10-07 1977-10-07 Timing logic circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP59152905A Division JPS60157333A (en) 1984-07-25 1984-07-25 Random access memory

Publications (1)

Publication Number Publication Date
JPS5453956A true JPS5453956A (en) 1979-04-27

Family

ID=14777878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12009977A Pending JPS5453956A (en) 1977-10-07 1977-10-07 Timing logic circuit

Country Status (1)

Country Link
JP (1) JPS5453956A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014194839A (en) * 2014-04-18 2014-10-09 Fujitsu Semiconductor Ltd Logic circuit and memory using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014194839A (en) * 2014-04-18 2014-10-09 Fujitsu Semiconductor Ltd Logic circuit and memory using the same

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