JPS54104272A - Complementary mos logic circuit - Google Patents
Complementary mos logic circuitInfo
- Publication number
- JPS54104272A JPS54104272A JP1052278A JP1052278A JPS54104272A JP S54104272 A JPS54104272 A JP S54104272A JP 1052278 A JP1052278 A JP 1052278A JP 1052278 A JP1052278 A JP 1052278A JP S54104272 A JPS54104272 A JP S54104272A
- Authority
- JP
- Japan
- Prior art keywords
- logic circuit
- terminal
- power consumption
- time
- cmos logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 title 1
- 230000008054 signal transmission Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Power Sources (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To make it possible to reduce the power consumption of a CMOS logic circuit, by reducing the power at the stand-by time while no logical operation is done, by making the CMOS logic circuit operate intermittently. CONSTITUTION:During logical operation, clock pulse (a) is supplied from input terminal 4 to terminal 6 via AND gate 2. When there is the latency time of logic circuit 1 from prescribed logic operation until the start of the next operation, clock forbidden signal (b) is generated from output terminal 7 to hold output O of flip- flop circuit 3 at level ''0'' and to inhibit a clock signal from passing through AND gate 2, thereby preventing the transmission of signals to terminal 7. The CMOS logic circuit therefore stops operating as shown by (e) until a reset signal is inputted to flip-flop circuit 3 and, in consequence, average power consumption at the stand- by time can almost be ignored, so that the reduction of power consumption can be realized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1052278A JPS54104272A (en) | 1978-02-03 | 1978-02-03 | Complementary mos logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1052278A JPS54104272A (en) | 1978-02-03 | 1978-02-03 | Complementary mos logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54104272A true JPS54104272A (en) | 1979-08-16 |
Family
ID=11752565
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1052278A Pending JPS54104272A (en) | 1978-02-03 | 1978-02-03 | Complementary mos logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54104272A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6140630A (en) * | 1984-07-26 | 1986-02-26 | マイルス・インコーポレーテッド | Clock circuit for microcomputer and control of time of microcomputer using the same |
JPH023884A (en) * | 1988-06-21 | 1990-01-09 | Toppan Printing Co Ltd | Ic card |
JPH04215112A (en) * | 1990-12-13 | 1992-08-05 | Nec Corp | Microcomputer |
WO2011052383A1 (en) * | 2009-10-30 | 2011-05-05 | Semiconductor Energy Laboratory Co., Ltd. | Logic circuit and semiconductor device |
US9748436B2 (en) | 2009-11-27 | 2017-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
1978
- 1978-02-03 JP JP1052278A patent/JPS54104272A/en active Pending
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6140630A (en) * | 1984-07-26 | 1986-02-26 | マイルス・インコーポレーテッド | Clock circuit for microcomputer and control of time of microcomputer using the same |
JPH0416805B2 (en) * | 1984-07-26 | 1992-03-25 | Miles Inc | |
JPH023884A (en) * | 1988-06-21 | 1990-01-09 | Toppan Printing Co Ltd | Ic card |
JPH04215112A (en) * | 1990-12-13 | 1992-08-05 | Nec Corp | Microcomputer |
US9722086B2 (en) | 2009-10-30 | 2017-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Logic circuit and semiconductor device |
CN106057819A (en) * | 2009-10-30 | 2016-10-26 | 株式会社半导体能源研究所 | Logic circuit and semiconductor device |
WO2011052383A1 (en) * | 2009-10-30 | 2011-05-05 | Semiconductor Energy Laboratory Co., Ltd. | Logic circuit and semiconductor device |
JP2017175137A (en) * | 2009-10-30 | 2017-09-28 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP2018137460A (en) * | 2009-10-30 | 2018-08-30 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US9748436B2 (en) | 2009-11-27 | 2017-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20190109259A1 (en) | 2009-11-27 | 2019-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10396236B2 (en) | 2009-11-27 | 2019-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and display device |
US11894486B2 (en) | 2009-11-27 | 2024-02-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
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