JPH04215112A - Microcomputer - Google Patents

Abstract

PURPOSE:To stop or start to supply the operation clock to a microcomputer which is generated externally. CONSTITUTION:A flip flop 110 is set when the microcomputer is set to the stop state, and it is reset when the microcomputer is released from the stop state. In accordance with the output value of this flip flop 110, a transfer gate 115 is turned on and a transfer gate 114 is turned off to stop the generation of an internal clock when the microcomputer is in the stop state. When the microcomputer is released from the stop state, the transfer gate 115 is turned off and the transfer gate 114 is turned on to start the generation of the internal clock. The output value of the flip flop 110 is outputted to the external also to stop or start the supply of the external clock or the clock generation itself.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a type of microcomputer that has a standby function and further generates a clock for operation based on input from an external crystal oscillator or an external clock generation circuit. .

0002

2. Description of the Related Art Microcomputers (hereinafter referred to as microcomputers) include a type called a single-chip microcomputer (or one-chip microcomputer, etc.) that has a built-in peripheral circuit. Peripheral circuits include interrupt controllers, DMA (direct memory access) controllers, timers, serial interfaces, etc., and control various systems.

[0003] Microcomputers are usually equipped with a function called a standby function. For example, if we assume a printer as a system device that uses a microcomputer, control processing is performed such as receiving data from an external device such as a personal computer, processing the received data by the microcomputer, and then passing it to the printing unit for printing processing. . In these cases,
The microcontroller performs the above operations only when data is sent from an external device, and at other times, the microcontroller has a standby function that stops the clock supplied to the microcontroller and stops internal operations in order to reduce power consumption. It is prepared for. Below, a conventional microcomputer equipped with the above-mentioned standby function will be explained in detail.

FIG. 4 shows the configuration of a conventional system device 300. The system device 300 includes a microcomputer 301, various peripheral devices 320, 321 such as timers, and the microcomputer 3
01, and a crystal oscillator 305 for the microcomputer to generate a clock for operating the microcomputer.

The microcomputer 301 includes a CPU 302 and built-in peripheral circuits 30 such as a timer and a serial interface.
3, and the above CPU to operate the entire microcomputer 301.
302 and a clock control circuit 30 that generates a system clock supplied to the built-in peripheral circuit 303.
It is composed of 4.

The CPU 302 and built-in peripheral circuit 303 each execute various instructions or perform control specific to each peripheral function based on the system clock supplied from the clock control circuit 304. In addition, the CPU
302 and the built-in peripheral circuit 303 are connected by an internal bus (not shown).

Next, the operation of clock control circuit 304 will be explained. The clock control circuit 304 has an X1 terminal 3
When the crystal resonator 305 is connected to the 30, The clock obtained on this signal line 308 is CLKOUT
Output from terminal 332 to external peripheral devices 320, 321
The frequency is divided by the frequency divider 311 and the CPU
The signal is supplied to the entire microcomputer 301 starting from 302.

[0008] Here, set/reset type flip
The flop 310 is in a state where the microcomputer 301 stops supplying the system clock to the entire microcomputer 301 (
Flip to indicate the STOP state).
It's a flop. When the CPU 302 executes the STOP command, the CPU 302 waits until the internal operating state of the microcomputer 301 reaches a state where it can transition to the STOP state. When it becomes possible for the inside of the microcomputer 301 to transition to the STOP state, the CPU 302 activates the signal 309. Flip-flop 310 is set by activation of signal 309. Conversely, if a signal to cancel the STOP state, such as a reset signal from the RESET terminal 334 or a non-maskable interrupt request signal from the NMI terminal 335, is input, the flip-flop 31
0 is reset. When the microcomputer 301 attempts to transition to the STOP state, the flip-flop 310 is set, so the output of the inverter 316 becomes "0". Therefore, the output value of the NAND gate 317 becomes "1", and the clock obtained on the signal line 308 is masked and is not output. Therefore, the output value from the CLKOUT terminal 332 via the buffer 318 is “
1". On the other hand, when attempting to release the STOP state, the flip-flop 310 is reset and the output value of the inverter 316 becomes "1". Therefore, the CLK
The clock obtained on the signal line 308 is output as is from the OUT terminal 332.

[0009] Also, transfer gates 314, 31
5 is provided to prevent the signal lines 312 and 313 from reaching an intermediate level when the microcomputer 301 enters the STOP state. Microcomputer 301 is STOP
When the output value of the flip-flop 310 becomes "1", the transfer gate 315 becomes O.
Therefore, the signal line 312 is fixed at a low level. On the other hand, since the transfer gate 314 is turned off, the signal line 313 is fixed at a high level.

As described above, the clock control circuit outputs a clock from the CLKOUT terminal 332 when the microcomputer 301 is in the normal state, and stops the clock output when the microcomputer 301 is in the STOP state. 304 is controlling.

Here, as shown in FIG. 5, the clock control circuit 304 has a configuration that can be applied to a case where a clock is input from an external clock generation circuit 405 instead of a crystal resonator. In this case, it is common practice to input the clock generated by the external clock generation circuit 405 to the X1 terminal 330, and input the inverted clock of the clock input to the X1 terminal 330 to the X2 terminal 331. A clock having the same phase as the clock input from the X2 terminal 331 can be obtained on the X2 terminal 308 . Also, when the external clock generation circuit 405 is used, the microcomputer 301 can also
When the P state is reached, the clock output from the CLKOUT terminal 332 is stopped under the control of the clock control circuit 304.

Furthermore, in the prior art, some microcomputers are equipped with an instruction emulation function and output a status indicating that the microcomputer is in the STOP state. In the case of such microcontrollers, even when the CPU executes a STOP instruction, the clock generation section inside the microcontroller does not stop generating the clock, and when the CPU executes the STOP instruction, the instruction is decoded and the STOP state is entered. The CPU activated a status signal indicating this. Also,
When an input signal is input from the RESET terminal or the NMI terminal, the clock generation section starts supplying the operating clock and then deactivates the CPU status signal indicating that the STOP state has been released. .

[0013]

[Problems to be Solved by the Invention] In the microcomputer equipped with the conventional clock control circuit described above, when the microcomputer enters the STOP state as described above, the transfer gate 315 is turned on and the transfer gate 3
14 turns off, the signal line 312 goes low.
The signal line 313 is fixed at a high level to prevent these signal lines from reaching an intermediate level. Here, when the clock is input from the external clock generation circuit 405, the clock generated by the external clock generation circuit 405 is input from the X1 terminal 303 and the X2 terminal 331 even when the microcomputer 301 is in the STOP state. There is. However, when the level of the clock input from the X1 terminal 330 becomes high level, a huge amount of current flows through the signal line 312 because the transfer gate 315 is ON, causing a short circuit. be.

Furthermore, even if the inside of the microcomputer enters the STOP state, the external clock generation circuit 405 does not stop generating clocks. Therefore, when the microcontroller enters the STOP state, C
Using the fact that the output of the LKOUT terminal 332 becomes "1", the CLKOUT terminal can be monitored and the external clock generation circuit can be stopped when it is detected that it continues to output "1". However, the external clock generation circuit 4
Even if it is possible to stop 05, the ST of the microcomputer
Since there is no means to detect in real time that the OP state has been released, the operation of the external clock generation circuit 405 cannot be restarted, and as a result, when the microcontroller enters the STOP state, the external clock generation circuit 405 cannot be restarted. could not be stopped.

[0015] Furthermore, in a microcontroller that has an instruction emulation function and outputs a status indicating that the microcontroller is in the STOP state, when an external clock generation circuit is used to supply the system clock, the STOP state is detected as described above. Although it is possible to judge the indicated status externally to the microcontroller and stop the external clock generation circuit,
Since there is no means for externally detecting in real time that the STOP state of the microcomputer has been released, the operation of the external clock generation circuit could not be resumed in this case as well. Therefore, a problem has arisen in that power consumption cannot be reduced even if the STOP state is entered.

[0016]

[Means for Solving the Problems] The microcomputer of the present invention can generate a system clock for its operation internally, or input the system clock from an external clock generation circuit. In either case, the system
In a microcomputer equipped with a clock generation means configured to supply a clock, the clock generation circuit is activated by a command from the microcomputer.
Holding means that is set when the clock supply is stopped and reset when the system clock supply is restarted by an external input signal, and an output that outputs the contents of the holding means to the outside. By externally determining the output value from the output means, the system clock can be generated internally in the microcomputer, or the system clock can be input from an external clock generation circuit. , a means for stopping the generation of the system clock by the clock generating means in response to an instruction from the microcomputer, and a means for determining the output value from the output means externally, thereby determining whether the system clock is generated internally in the microcomputer or externally. In either case, the system clock is inputted from the clock generating circuit of the clock generating circuit, and means for restarting the generation of the system clock by the clock generating means in response to an input signal from the outside.

Therefore, when a clock is input from an external clock generating means, the microcomputer
It is possible to detect externally that the TOP state has been reached or that the STOP state has been released, and to stop or restart the supply of an externally generated clock to the microcomputer.

[0018]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

A first embodiment of the microcomputer of the present invention will be described with reference to FIG. System device 1
00 is a microcomputer 101 and various peripheral devices 1 such as timers.
20, 121, and an external clock generation circuit 105 that generates a clock for operating the microcomputer 101 and supplies it to the microcomputer 301.

The microcomputer 101 includes a CPU 102 and built-in peripheral devices 10 such as a timer and a serial interface.
3, and the above CP in order to operate the entire microcomputer 101.
The clock control circuit 104 supplies a system clock to U102 and built-in peripheral circuit 103 to generate a system clock.

[0021] The CPU 102 is the clock control circuit 10 described above.
Various instructions are executed based on the system clock supplied from 4. Moreover, the built-in peripheral circuit 103 is
For example, in the case of a timer, the timer counter counts based on the system clock, and in the case of a serial interface, for example, serial data is input/output based on the system clock, etc., supplied from the clock control circuit 104. Control is performed based on the system clock. Note that the CPU 102 and the built-in peripheral circuit 103 are connected by an internal bus (not shown).

Next, the operation of the clock control circuit 104 will be explained. The clock control circuit 104 is configured to obtain a clock on a signal line 108 by a resistor 106 and an inverter 107 when a crystal resonator/ceramic oscillator is connected to the input terminals X1 terminal 130 and X2 terminal 131. This configuration can also be applied when a clock is input from an external clock generation circuit as in this embodiment. The clock output from the external clock generation circuit 105 is input to X1 via an AND gate 124, which will be described later.
A clock input from the terminal 130 is input from the X2 terminal 131, and a clock which is inverted from the clock input from the X1 terminal 130 is input from the X2 terminal 131. The clock control circuit 104 uses this X1 terminal 130
Based on the clock input from the X2 terminal 131, a clock having the same phase as the clock input from the X2 terminal 131 is obtained on the signal line 108. The clock obtained on this signal line 108 is CLKOUT via a buffer 118.
Output from terminal 132 to external peripheral devices 120, 121
At the same time, the frequency is divided by a frequency divider 111 and supplied to the entire microcomputer 101 including the CPU 102 as a system clock.

Here, set/reset type flip
The flop 110 is a flip-flop that indicates that the microcomputer 101 is in the STOP state. CPU102
When the STOP command is executed, the microcomputer 101 waits until the internal operating state of the microcomputer 101 reaches a state where it can transition to the STOP state. For example, when attempting to transition to the SOTP state, the D
If the MA controller is in the process of transferring data, it waits until the data transfer is completed. After the data transfer is completed, the microcomputer 101
When it becomes possible for the internal state to transition to the STOP state, CPU 102 activates signal 109 and sets flip-flop 110. Conversely, RESET terminal 13
4 and the non-reset signal from NMI terminal 135.
When a signal for canceling the STOP state, such as a maskable interrupt request signal, is input, the flip-flop 110 is reset. When the microcomputer 101 attempts to transition to the STOP state, the flip-flop 110 is set, so the output value of the inverter 116 becomes "0". Therefore, the output value of the NAND gate 117 becomes "1", and the clock obtained on the signal line 108 is masked and not output. Therefore, the output value from the CLKOUT terminal 132 via the buffer 118 is “1”.
”. On the other hand, when attempting to release the STOP state by the above-mentioned reset signal non-maskable interrupt request signal, the flip-flop 110 is reset and the output value of the inverter 116 becomes “1”.
The clock obtained on the signal line 108 is output as is from the LKOUT terminal 132.

On the other hand, the output of the flip-flop 110 is outputted to the outside from the STOPS terminal 133 via the inverter 122. When the microcomputer 101 is in the STOP state, the output value of the flip-flop 110 is "1", so the STOPS terminal 133 outputs a low level. Conversely, when the microcomputer 101 is not in the STOP state,
Since the output value of the flip-flop 110 is "0", the STOPS terminal 133 outputs a high level. The AND gate 124 inputs the output value from the STOPS terminal 133 and the output value from the external clock generation circuit 105, and sends the output value to the X1 terminal 1 of the microcomputer 101.
30 is entered. When the microcomputer 101 is not in the STOP state, the output value from the STOPS terminal 133 is high.
Therefore, the clock output from the external clock generation circuit 105 is input to the X1 terminal 130 as it is. The clock input to the X1 terminal 130 and the inverted clock are input to the X2 terminal 131 . Furthermore, when the microcomputer 101 is in the STOP state, the output value from the STOPS terminal 133 is at a low level, so the clock output from the external clock generation circuit 105 is masked.
A low level is always input to the X1 terminal 130. X
A high level is always input to the second terminal 131. R.E.
Reset signal from SET terminal 134 and NMI terminal 13
When a non-maskable interrupt request signal etc. from 5 is input, the flip-flop 110 is reset and the
The TOPS terminal 133 becomes high level again. Therefore, the clock output from the external clock generation circuit 105 is input as is to the X1 terminal 130, and the
A clock input to the X1 terminal 130 and an inverted clock is input to the input terminal 31.

Transfer gates 114 and 115 connect signal line 11 when microcomputer 101 is in the STOP state.
This is provided to prevent the number 2,113 from becoming an intermediate level. The microcomputer 101 is about to transition to the STOP state and the output value of the flip-flop 110 is “
1”, the transfer gate 115 turns on,
Transfer gate 114 is turned off. At this time,
As mentioned above, a low level is input to the X1 terminal 130 and a high level is input to the X2 terminal 131, so the signal line 112 is at a low level and the signal line 11 is at a low level.
3 is fixed at high level. RESET terminal 134
When a reset signal from the NMI terminal 135 or a non-maskable interrupt request signal from the NMI terminal 135 is input, the flip-flop 110 is reset, so the transfer gate 115 turns OFF and the transfer gate 11
4 is ON. At this time, as mentioned above, the X1 terminal 13
Since the clock that is the output from the external clock generation circuit 105 is inputted from the 0 and X2 terminals 131, the clock is again obtained on the signal line 108, and the
At the same time, the clock is output from the CLKOUT terminal 132 to the outside.

FIG. 3 is a timing chart showing the above-mentioned operation.

In this manner, when the microcomputer 101 is operated by the external clock, the microcomputer 101 operates from the ST
In the OP state, the clock output from the CLKOUT terminal 132 is stopped, and the STOPS terminal 13
3 is inactivated to stop inputting the external clock. Furthermore, when an attempt is made to release the STOP state, the STOPS terminal 133 is activated, so the external clock is input again from the X1 terminal 130 and the Clock is output.

A second embodiment will be explained using FIG. 2. The configuration of this embodiment is almost the same as that of the previous embodiment, so only the different parts will be explained.

STOPS indicating the STOP state
The state of the terminal 133 is input to the AND gate 124 via the signal line 127 and is also transmitted to the external clock generation circuit 105. When the output from the STOPS terminal 133 becomes low level, that is, the microcomputer 101
When attempting to transition to the OP state, the external clock generation circuit 105 stops generating clocks. Also, STOP
When the output from S terminal 133 becomes high level,
That is, when the microcomputer 101 attempts to release the STOP state, the external clock generation circuit 105 restarts clock generation.

The operation timing chart is similar to that shown in FIG.

[0031]

As described above, a microcomputer equipped with the clock control circuit of the present invention can externally determine whether or not the microcomputer itself is in the STOP state.

For this reason, when a system is adopted in which a clock is generated externally and the clock is supplied to the microcomputer, even if the microcomputer enters the STOP state, the clock supplied from the outside is determined based on the determination result of the STOP state. This can prevent short circuits caused by internal gates turning on.

Furthermore, it is possible to stop external clock generation itself based on the determination result of the STOP state.
When entering the OP state, the power consumption of the entire system including the microcomputer can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system device including a microcomputer including a clock control circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a system device including a microcomputer including a clock control circuit according to a second embodiment of the present invention.

FIG. 3 is an operation timing chart of the clock control circuit.

FIG. 4 is a block diagram of a system device including a microcomputer including a conventional clock control circuit.

FIG. 5 is a block diagram of a system device including a microcomputer including a conventional clock control circuit.

Claims (1)

[Claims] Claim 1: A system clock for operating a microcomputer is generated internally, and a system clock is generated from an external clock generation circuit.
The system clock is input in both cases.
In a microcomputer equipped with a clock generation means configured to supply a clock, this is set when the clock generation circuit stops supplying the system clock by an instruction, and is set when the clock generation circuit stops supplying the system clock by an input signal from the outside. The system clock is controlled by a microcontroller by using a holding means that is reset when clock supply is restarted, an output means that outputs the contents of the holding means to the outside, and an external judgment of the output value from the output means. means for stopping the generation of the system clock by the clock generation means according to instructions from a microcomputer, whether the system clock is generated internally in the computer or inputted from an external clock generation circuit; By determining the output value from the output means externally, the system clock can be output from the outside regardless of whether the system clock is generated internally within the microcomputer or when the system clock is input from an external clock generation circuit. A microcomputer comprising means for restarting the generation of a system clock by the clock generation means in response to an input signal.