JPS57116432A - Synchronous counter - Google Patents

Abstract

PURPOSE:To decrease the number of elements and to reduce power consumption greatly by simplifying a circuit by using as a state inversion control signal each of output signals of MOS transistors (TR) which are provided in series and each receive the output of a prescribed stage of an FF as a gate input. CONSTITUTION:An FF1 is set and reset repeatedly at the rising timing of a clock pulse CP. Its set output Q1 and reset output Q1' turn on MOSTRs 1 and 4 respectively. Therefore, an inversion control signal C2 appearing at the output terminal n1 of the TR1 has a signal waveform similar to that of the output Q1 of the FF11. While this signal C2 is generated, an FF12 is set and reset at the rising timing of the pulse CP, so an inversion control signal C3 appearing at the output terminal of a TR2 has pulses a half as many as the signal C2 has. Thus, a state inversion control signal Ci for FFs 11-14 goes up to 1 when FF outputs of preceding stages are all at 1, and the FFs 11-14 repeat hexadecimal up- counter operation. Consequently, the number of elements of a state inversion control circuit for the FFs is decreased.