JPS5673923A - Signal generating circuit for ccd drive - Google Patents
Signal generating circuit for ccd driveInfo
- Publication number
- JPS5673923A JPS5673923A JP15127079A JP15127079A JPS5673923A JP S5673923 A JPS5673923 A JP S5673923A JP 15127079 A JP15127079 A JP 15127079A JP 15127079 A JP15127079 A JP 15127079A JP S5673923 A JPS5673923 A JP S5673923A
- Authority
- JP
- Japan
- Prior art keywords
- output
- flop
- flip
- shift register
- fed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- H03K5/15093—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using devices arranged in a shift register
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
PURPOSE:To obtain the timing pulse for CCD drive with less constituent elements, by a shift register in 4 bits, a JK flip-flop and AND gates connected to the shift register. CONSTITUTION:When a reference clock pulse CP is fallen, after a reset pulse RES is fallen down, the 1st stage flip-flop 1a of a shift register 1 reads in a logic 1 and this is fed to flip-flop 1b-1d of the next state every time CP is fallen. When the final stage 1d reads in it and Q4 output is at ''1'', the operation of inverting the Q output as 0,1 by a JK flip-flop is repeated, until RES is incoming, to produce the shift clocks phi1, phi2. On the other hand, the inversion Q4 output and Q3 output of the shift register 1 are fed to an AND gate 4, and the Q1 output and inversion Q2 output are fed to an AND gate 3, to respectively produce the clocks phiXA and phiXB.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15127079A JPS5673923A (en) | 1979-11-20 | 1979-11-20 | Signal generating circuit for ccd drive |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15127079A JPS5673923A (en) | 1979-11-20 | 1979-11-20 | Signal generating circuit for ccd drive |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5673923A true JPS5673923A (en) | 1981-06-19 |
Family
ID=15514990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15127079A Pending JPS5673923A (en) | 1979-11-20 | 1979-11-20 | Signal generating circuit for ccd drive |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5673923A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009118875A (en) * | 2007-11-10 | 2009-06-04 | Tomoko Yanagisawa | Cover for urethral catheterization bag |
-
1979
- 1979-11-20 JP JP15127079A patent/JPS5673923A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009118875A (en) * | 2007-11-10 | 2009-06-04 | Tomoko Yanagisawa | Cover for urethral catheterization bag |
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