SU542337A1 - Discrete Random Timer - Google Patents

Description

frequencies, each bit of which contains two keys, the outputs of which are connected to inputs 3 -K of a flip-flop, the counting input of which is connected via the OR element to the output of the AND element, and the outputs of the random pulse generator are connected to the first inputs of the keys of the first bit of the frequency divider, and the input of the generator is connected to the second input of the element AND of the first bit of the frequency divider, while the outputs of the 3-K trigger of each previous bit of the frequency divider are connected to the inputs of the subsequent keys, the output of the element OR the previous one present discharge is connected to a second input of AND later, and outputs

D-K - the trigger and the element OR of the last bit are connected to the first and second inputs of the output element AND, the second output of the clock frequency generator is connected through the input element AND to the second input of the element OR the first bit of the frequency divider, the second input of the input element AND is connected to the first trigger output and through the output element And with the first input of the same trigger, the second input of which is connected to the second output of the clock frequency generator, and the second output of the trigger is connected to the second inputs of the keys of all bits of the divider part From the first input of the element AND of the first bit, the output of which is connected to the second inputs of the elements OR of all the bits except the first.

The drawing shows a structural electrical driver circuit.

The discrete (nd random time interval shaper contains a clock frequency generator 1, connected to a random pulse generator 2, trigger 3, T is a bit frequency divider 4, input 5 and output 6 are elements And

Frequency divider 4 includes bits 7–7, each of which

contains keys 8 and 9, the outputs of which are connected to inputs 3 -K - trigger 10, the counting input of which is connected through the element OR 11c output element And 12,

The outputs of the generator of a random sequence of pulses 2 are connected to the first inputs of keys 8, 9 of the first bit 7, frequency divider 4, the generator input is connected to the second input of the element 12 of the first bit 7 divider. Outputs D-K - trigger 10 of each previous bit of the frequency divider are connected to the inputs of keys 8 and 9 of the next bit. The output of the element OR 1 of the previous bit is connected to the second input of the element AND 1.2 next. The outputs D - K - trigger 10 and the element OR 11 of the last bit 7, the divider is connected to the first and second inputs of the output element AND 6,

The second output of the clock frequency generator 1 is connected through the input element AND 5 to the second input of the element OR 11 of the first bit 7, frequency divider 4,

The second input of the input element And 5 is connected to the first output of the trigger 3 and through the output element And 6 to the first input of the trigger, the second input of which is connected to the second output of the clock frequency generator 1,

The second output of the trigger 3 is connected to the second inputs of the keys 8 and 9 of all bits 7 of the frequency divider 4 and to the first input of the And 12 element of the first bit 7- (divider.

The output of the element And 12 of the first bit 7J is connected to the second inputs of the elements OR 11 of all bits of the divider, except the first.

Discrete shaper random intervals of time works as follows.

After the appearance at the output of the element 6 of the pulse 3, it goes into the single state and opens the keys 8, 9 of all bits of the frequency division 4, which then switches to the tl-bit register mode. A random sequence, fork-: generated by a generator of a random sequence of pulses 2, with a clock frequency F is fed through public keys 8 and 9 to the inputs U-K - flip-flops 10, B the register is written to the digit number. At the same time, the clock pulses with a frequency P through the open element 12 of the first bit 7 frequency divider to the elements OR 11 all bits arrive as a shift frequency on the registers formed by the trigger 10 of the divider.

After a time interval T (P is the number of bits of the frequency divider; after the occurrence of n: and output 6 of the counting pulse, the clock frequency generator 1 outputs the next frequency pulse f i-ia trigger trigger 3. In this case, the trigger goes to the zero state, the keys 8, 9 all bits and the element And 1 of the first bit 7 frequency divider

are closed, and the element And 5 opens

and the register is switched to the frequency divider mode.

At the entrance of the first category yes 7

divider

frequencies begin to arrive counting pulses.

By the time the register is switched to the divider mode, some random AND — bit digit K is written into it. Now, at the output of the divider, a pulse appears when it arrives at its input with m-PULSES with a frequency of f-7 where the divider is divided. Since K is a random number, it is also a random number.

After the appearance of the next pulse at the output of the AND 6 element, the frequency divider 4 switches to the shift register mode, and a random number K is recorded for one period of one frequency pulse f, after which the divider is transferred to the counting mode, and pulses from clock frequency generator 1 with frequency f.

Claims (2)

1. Avt.Sv. USSR № 328527, cl. H 03 K 5/156, 24.03.70. 2. Avt.sv, USSR № 496664, cl. H 03 K 3/64, 07.06.73.