SU564715A1 - Delayed-pulse multichannel oscillator - Google Patents

Description

(54) MULTI-CHANNEL GENERATOR OF CLUSED PULSE DELAYED CL / B, the second INPUT of which is connected to the input. The device bus is connected with the output, and the output is connected to the input of the control register and the control input of the memory information of the storage device. The main output of the control register is connected to the third input of the hecherator clock pulses, with the output impedance and with the output bus of the formation canon, to the additional outputs of the control register are connected to the address inputs of the storage device and the switch, the inputs of which are connected to the input canals of the hopper jacks. connection to the input of the detracting counter, the installation inputs of which are connected to the outputs of the storage device. FIG. 1 shows a structural electrical circuit diagram of the device; 2, voltage plots at individual points of the circuit in one of the channels: 2 (f at the device input; 2b at the output of the clock generator; at the output, a zero state latch of the reading counter 2, at the main output of the control register; 2Q, w and h at the additional outputs of the control register; 2 U-at the output of the output impedance shaper The device consists of 1 reference frequency generator, serially connected dividers 2, D,, ... 2 frequencies, channels 3j, Sg ... 3 | the formation of delayed pulses, each of which contains a memory The output device 4, the output impulse factorizer 5, the code comparison device 6, consisting of the switch 7, the four-bit subtraction counter 8, the zero-state latch 9, the generator 1 O TOBbtx of the control register pulses, the control register 11. The device has an input 12 and two outputs in each channel of 13-, 13-l, ... ISj and 14, 14. of which, connected to the main output of the control register 11, is connected through the element OR 15 to the control input generator 1, reference frequency. Works multichannel generator delayed pulses as follows. In the initial state, the subtractive counters 8 in the channel are zeroed, the main and additional outputs of the control registers 11 have a low potential, therefore, the operation of the 1 st oscillator frequency and the generators is blocked. U clock pulses in the channels, as well as dubbing from the storage device 4 and the passage of pulses through the switches 7 to the inputs of the subtracting counters 8 pulses in each channel, the memory devices recorded the values of delays. The operation of the device begins when the starting impulse arrives at the device input (see Fig. 2, moment id). At the same time, a high potential appears in the outputs of the generators u in each channel. The conversion of the codes into the pulse delay time intervals begins at the end of the starting pulse at the time instant. The moment of time is characterized by a negative voltage drop at the generator output of 10 clocks, as a result of which the unit in the control register 11 is shifted, a high potential appears at the output 14 and the lowest additional output of the control register 11; the higher nibble of the converted code is rewritten from memory 4 to subtractive counter 8, the reference frequency generator 1 is connected via the OR 15 element, the switch 7 connects to the input of the subtractive counter 8 the corresponding (lowest frequency) output of the splitter 2 frequency The state of the counter, in the presence of units in a variable nibble, is a high potential that blocks the operation of the generator of clock pulses. Then, the pulses from the divider 2 to the subtracting counter 8 are counted. At the moment i, when the number of incoming pulses becomes equal to the number rewritten from the memory, the zero-state lock of the counter turns on the generator of 10 pulses. As a result, the next nibble is rewritten from the storage device 4 to the counter 8, and the input of the counter 8 is connected to the output of the previous divider 2. The lethal half-bytes are treated similarly. If the next nibble rewritten into counter 8 is not contained in the code, the generator 10 clock pulses generates a new pulse, and the next nibble is processed in the channel (see Fig. 2, times tj: And t). In the last cycle, the lower nibble of the code to be converted is processed (see Fig. 2, time interval i -). At the same time, the input of the counter 8. is connected directly to the output of the generator 10 of the reference frequency. Edited by B. Fedotov / Tehred A. Dem5tov Proofreader A, Vlasenko

Order 2062/217 Circulation L.065 Subscription

TsNIIPI State Committee of the USSR Council of Ministers

Deposits of inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Fipiap PPP Patent, Uzhgfod, unitary enterprise. Project, 4

The composition of V. Nazarov