EP0113935A3 - Timer circuit - Google Patents

Abstract

In order to obtain a high time resolution a timer circuit comprises a clock pulse generator arrangement (47) an output of which feeds the input (3) of a delay line (4) which is provided with n taps (9) the positions of which correspond to substan­ tially equal increments T of delay. The mark-to-space ratio of the pulses fed to the delay line is unity and their period such that exactly one can be accommodated in the delay line. The taps are connected to a latch (10) which is clocked from an in­ put (46) when an event occurs the time of occurrence of which it is required to record. The Johnson code appearing at the latch output (12-19) is converted to binary by means of a de­ coder (28) and fed to an output (39). The arrangement also in­ cludes a coarse counter (7) the least significant bit of which has the same significance as, and is nominally synchronised with, the most significant bit of the binary code. In order to re­ solve ambiguities which might otherwise occur when the event occurs near to an all-1s to 0s transition of the binary code the current count and the previous count of the coarse counter are held in a pair of registers (34, 37). Which of these counts is ap­ propriate at any given time is determined by comparing the same-significance bits of the coarse and fine counts in an ex­ clusive-or gate (41) the output of which gates the output (35 or 38) of the appropriate register to the circuit output (39).