CN101515155B

CN101515155B - Time-to-digital conversion circuit and related method thereof

Info

Publication number: CN101515155B
Application number: CN2008100807848A
Authority: CN
Inventors: 陈逸琳
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2008-02-18
Filing date: 2008-02-18
Publication date: 2010-10-13
Anticipated expiration: 2028-02-18
Also published as: CN101515155A

Abstract

A time-to-digital conversion circuit, comprising: a first delay circuit having a first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit having a second delay stage for delaying a second input signal to generate a second output signal; a first counter for counting the first output signal to generate a first count value; the second counter is used for counting the second output signal to generate a second counting value; and a comparator for comparing the first count value with the second count value to generate a comparison result signal; the first delay stage has a larger delay amount than the second delay stage, the first counter starts counting earlier than the second counter, and the comparator outputs a comparison result signal when the second count value falls within a predetermined range including the first count value.

Description

Time-to-digital conversion circuit and correlation technique thereof

Technical field

The invention relates to time-to-digital conversion circuit, be particularly to use delay circuit to produce the time-to-digital conversion circuit of cyclic delay signal.

Background technology

Generally speaking, time-to-digital conversion circuit (Time to Digital Converting, TDC) be delay degree, convert the retardation of actual delay-level to, just the delay degree of signal is represented with the delay-level of exact number with delay degree with signal in order to measuring-signal.The old practice is, respectively first signal and secondary signal are sent into first delay circuit and second delay circuit, wherein than secondary signal (being generally known reference signal) early but the retardation of the delay-level of first delay circuit is bigger than the retardation of the delay-level of second delay circuit time of sending into of first signal (being generally measured signal).Therefore, secondary signal can slowly catch up with first signal.And when secondary signal catch up with first signal, just can calculate the two signals delay-level quantity of process respectively, and calculate the difference total amount of two delay-level groups, just can calculate the delay degree of first signal.The common practice is, calculates the poor (t of the less delay-level tf of the bigger delay-level ts of retardation and retardation earlier with other mechanism _s-t _f), again with the delay situation of measured signal with N (t _s-t _f) expression.Since the structure and the mode of operation of this type time-to-digital conversion circuit, and how to calculate known to those skilled in the art knowing, so do not repeat them here.

Yet such practice often must use the delay circuit of whole piece, so circuit can have bigger area.

Summary of the invention

Therefore, a purpose of the present invention is for providing a kind of time-to-digital conversion circuit and correlation technique thereof, and it changes delay circuit originally into the cyclic delay circuit, to save circuit area.

Embodiments of the invention have disclosed a kind of time-to-digital conversion circuit, comprise: first delay circuit has at least one first delay-level, in order to postpone first input signal to produce first output signal; Second delay circuit has at least one second delay-level, in order to postpone second input signal to produce second output signal; First counter couples this first delay circuit, in order to count this first output signal to produce first count value; Second counter couples this second delay circuit, in order to count this second output signal to produce second count value; And comparer, couple this first counter and this second counter, in order to relatively this first count value and this second count value to produce compare result signal; Wherein this first delay-level has bigger retardation than this second delay-level, and this first counter early begins counting than this second counter, and when this second count value fell within the preset range that comprises this first count value, this comparer was exported this compare result signal.

Embodiments of the invention also disclose a kind of time figure conversion method, comprise: use at least one first delay-level to postpone first input signal to produce first output signal; Use at least one second delay-level to postpone second input signal to produce second output signal; Count this first output signal to produce first count value; Count this second output signal to produce second count value; And relatively this first count value and this second count value to produce compare result signal; Wherein this first delay-level has bigger retardation than this second delay-level, and this first count value early begins to be counted than this second count value, and when this second count value falls within the preset range that comprises this first count value, export this compare result signal.

Description of drawings

Fig. 1 has illustrated the time-to-digital conversion circuit according to the first embodiment of the present invention.

Fig. 2 has illustrated time-to-digital conversion circuit according to a second embodiment of the present invention.

[main element label declaration]

100,200 time-to-digital conversion circuits

101 first delay circuits

103 second delay circuits

105 first counters

107 second counters

109 comparers

111 AND doors

113 OR doors

115,117,119 first delay-level

121 AND doors

123 OR doors

125,127,129 second delay-level

201 control circuits

Embodiment

In the middle of instructions and above-mentioned claim, used some vocabulary to censure specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This instructions and above-mentioned claim are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be open term mentioned " comprising " in the middle of instructions and the above-mentioned request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " coupling " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other device or connection means if describe first device in the literary composition.

Fig. 1 has illustrated the time-to-digital conversion circuit 100 according to the first embodiment of the present invention.As shown in Figure 1, time-to-digital conversion circuit 100 comprises first delay circuit 101, second delay circuit 103, first counter 105, second counter 107 and comparer 109.First delay circuit 101 has at least one first delay-level 115,117,119, in order to postpone the first input signal In ₁To produce the first output signal Out ₁ Second delay circuit 103 has at least one second delay-level 125,127,129, in order to postpone the second input signal In ₂(being known reference signal in this example) is to produce the second output signal Out ₂Comparer 109 couples first counter 105 and second counter 107, in order to compare the first count value CV ₁With the second count value CV ₂To produce compare result signal CR.

Wherein first delay-level, 115,117,119 to the second delay-level 125,127,129 have bigger retardation, and first counter 105 early begins counting that is the first input signal In than second counter 107 ₁Than the second input signal In ₂Early be transfused to.In this embodiment, as the first count value CV ₁With the second count value CV ₂When equating, promptly can be considered the second input signal In ₂Caught up with the first input signal In ₁, comparer 109 can output compare result signal CR then.In one embodiment, comparer 109 can be external to predetermining circuit and compare result signal CR and uses as the trigger pip of predetermining circuit.Yet, as the first count value CV ₁With the second count value CV ₂Be not equal, and its gap is when only being small gap, also can ignores this gap and the second input signal In ₂Be considered as catching up with the first input signal In ₁, such variation also belongs to scope of the present invention.That is, as the second count value CV ₂Fall within and comprise the first count value CV ₁Preset range in the time, with the second input signal In ₂Be considered as catching up with the first input signal In ₁And comparer 109 output compare result signal CR.

In addition, first delay circuit 101 in this embodiment also comprises AND door 111 and OR door 113.Wherein AND door 111 receives reset signal RES, in order to the first output signal Out that resets ₁, and OR door 113 is coupled to AND door 111, in order to the output and the first input signal In according to AND door 111 ₁Output signal to first delay-level 115,117,119.Second delay circuit 103 also has AND door 121, OR door 123, second delay-level 125,127,129, and its structure is also identical with first delay circuit 101.Because first delay circuit 101 shown in Figure 1 and the detail operations mode of second delay circuit 103 are well known to those skilled in the art, so do not repeat them here.It is noted that first delay circuit 101 shown in Figure 1 and the structure of second delay circuit 103 are only in order to give an example the also applicable the present invention of the delay circuit of other structure.

According to the above embodiments, owing to be by the first count value CV ₁With the second count value CV ₂Judge the first input signal In ₁Whether catch up with the second input signal In ₂, and the first count value CV ₁With the second count value CV ₂Each count value is all represented more than one delay-level, therefore can save the area of delay circuit.For instance, if the first input signal In ₁With the second input signal In ₂Gap be n (t _s-t _f), then the delay circuit in known technology just needs n delay-level at least.But the cyclic delay circuit of time-to-digital conversion circuit is if having K delay-level according to an embodiment of the invention, and then each count value is just represented K (t _s-t _r), therefore just can

The delay circuit of times area is calculated identical gap.

Fig. 2 has illustrated time-to-digital conversion circuit 200 according to a second embodiment of the present invention.The element of embodiment shown in Figure 2 is similar with the framework of embodiment shown in Figure 1, and difference has been more than second embodiment shown in Figure 2 what delay-level control circuit 201 will produce output signal with to control first delay circuit 101 and second delay circuit 103.Therefore, the first output signal Out ₁With the second output signal Out ₂Can only corresponding first delay circuit 101 and second delay circuit 103 in the part delay-level, so can make the application of time-to-digital conversion circuit provided by the present invention more extensive.And, not necessarily will have control circuit 201 will produce output signal with what delay-level to select first delay circuit 101 and second delay circuit 103, those skilled in the art are when using other machine-processed control circuit 201 to select first delay circuit 101 and second delay circuit 103 to produce output signal with what delay-level.

Disclose according to an embodiment of the invention and also can obtain corresponding time figure conversion method, can be summarized as follows: use at least one first delay-level to postpone first input signal to produce first output signal; Use at least one second delay-level to postpone second input signal to produce second output signal; Count first output signal to produce first count value.Count second output signal to produce second count value; Relatively first count value and second count value are to produce compare result signal.

Other technical characterictic of the method can push away easily by above-listed description, so do not repeat them here.

The above only is embodiments of the invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. A time-to-digital conversion circuit comprising:

The first delay circuit has at least one first delay stage, which is used to delay the first input signal to generate the first output signal;

The second delay circuit has at least one second delay stage, which is used to delay the second input signal to generate the second output signal;

a first counter, coupled to the first delay circuit, for counting the first output signal to generate a first count value;

a second counter, coupled to the second delay circuit, for counting the second output signal to generate a second count value; and

a comparator, coupled to the first counter and the second counter, for comparing the first count value and the second count value to generate a comparison result signal;

Wherein the first delay stage has a larger delay amount than the second delay stage, and the first counter starts counting earlier than the second counter, and when the second count value falls below the value containing the first count value When within the predetermined range, the comparator outputs the comparison result signal.

2. The time-to-digital conversion circuit according to claim 1, wherein the comparator outputs the comparison result signal when the second count value is equal to the first count value.

3. The time-to-digital conversion circuit according to claim 1, wherein the comparator is coupled to a predetermined circuit, and the comparison result signal is used as a trigger signal of the predetermined circuit.

4. The time-to-digital conversion circuit according to claim 1, wherein the first delay circuit has a plurality of first delay stages, and the first output signal corresponds to a part of the first delay stages.

5. The time-to-digital conversion circuit according to claim 1, wherein the second delay circuit has a plurality of second delay stages, and the second output signal corresponds to a part of the second delay stages.

6. A time digital conversion method, comprising:

delaying the first input signal using at least one first delay stage to generate a first output signal;

delaying the second input signal using at least one second delay stage to generate a second output signal;

counting the first output signal to generate a first count value;

counting the second output signal to generate a second count value; and

comparing the first count value with the second count value to generate a comparison result signal;

Wherein the first delay stage has a larger delay amount than the second delay stage, and the first count value starts to be counted earlier than the second count value, and when the second count value falls within the range including the first When the count value is within a predetermined range, the comparison result signal is output.

7. The time-to-digital conversion method according to claim 6, wherein the step of comparing the first count value with the second count value to generate a comparison result signal is when the second count value is substantially equal to the first count value output the comparison result signal.

8. The time-to-digital conversion method according to claim 6, wherein the comparison result signal is used as a trigger signal of a predetermined circuit.

9. The time-to-digital conversion method according to claim 6, wherein the step of using at least one first delay stage to delay the first input signal to generate the first output signal is to use a plurality of first delay stages, and the first output The signals correspond to some of the first delay stages.

10. The time-to-digital conversion method according to claim 6, wherein the step of using at least one second delay stage to delay the second input signal to generate the second output signal is to use a plurality of second delay stages, and the second The output signal corresponds to a part of the second delay stages.