CN101515155B - Time-to-digital conversion circuit and correlation method thereof - Google Patents
Time-to-digital conversion circuit and correlation method thereof Download PDFInfo
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- CN101515155B CN101515155B CN2008100807848A CN200810080784A CN101515155B CN 101515155 B CN101515155 B CN 101515155B CN 2008100807848 A CN2008100807848 A CN 2008100807848A CN 200810080784 A CN200810080784 A CN 200810080784A CN 101515155 B CN101515155 B CN 101515155B
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Abstract
The invention provides a time-to-digital conversion circuit, which comprises a first delay circuit, a second delay circuit, a first counter, a second counter and a comparator, wherein the first delay circuit is provided with a first delay level and used for delaying a first input signal to generate a first output signal; the second delay circuit is provided with a second delay level and used for delaying a second input signal to generate a second output signal; the first counter is used for counting the first output signal to generate a first counting value; the second counter is used for counting the second output signal to generate a second counting value; the comparator is used for comparing the first counting value with the second counting value to generate a comparison result signal; the first delay level has larger delay quantity than the second delay level; the first counter begins to count earlier compared with the second counter; and when the second counting value is within a preset range comprising the first counting value, the comparator outputs the comparison result signal.
Description
Technical field
The invention relates to time-to-digital conversion circuit, be particularly to use delay circuit to produce the time-to-digital conversion circuit of cyclic delay signal.
Background technology
Generally speaking, time-to-digital conversion circuit (Time to Digital Converting, TDC) be delay degree, convert the retardation of actual delay-level to, just the delay degree of signal is represented with the delay-level of exact number with delay degree with signal in order to measuring-signal.The old practice is, respectively first signal and secondary signal are sent into first delay circuit and second delay circuit, wherein than secondary signal (being generally known reference signal) early but the retardation of the delay-level of first delay circuit is bigger than the retardation of the delay-level of second delay circuit time of sending into of first signal (being generally measured signal).Therefore, secondary signal can slowly catch up with first signal.And when secondary signal catch up with first signal, just can calculate the two signals delay-level quantity of process respectively, and calculate the difference total amount of two delay-level groups, just can calculate the delay degree of first signal.The common practice is, calculates the poor (t of the less delay-level tf of the bigger delay-level ts of retardation and retardation earlier with other mechanism
s-t
f), again with the delay situation of measured signal with N (t
s-t
f) expression.Since the structure and the mode of operation of this type time-to-digital conversion circuit, and how to calculate known to those skilled in the art knowing, so do not repeat them here.
Yet such practice often must use the delay circuit of whole piece, so circuit can have bigger area.
Summary of the invention
Therefore, a purpose of the present invention is for providing a kind of time-to-digital conversion circuit and correlation technique thereof, and it changes delay circuit originally into the cyclic delay circuit, to save circuit area.
Embodiments of the invention have disclosed a kind of time-to-digital conversion circuit, comprise: first delay circuit has at least one first delay-level, in order to postpone first input signal to produce first output signal; Second delay circuit has at least one second delay-level, in order to postpone second input signal to produce second output signal; First counter couples this first delay circuit, in order to count this first output signal to produce first count value; Second counter couples this second delay circuit, in order to count this second output signal to produce second count value; And comparer, couple this first counter and this second counter, in order to relatively this first count value and this second count value to produce compare result signal; Wherein this first delay-level has bigger retardation than this second delay-level, and this first counter early begins counting than this second counter, and when this second count value fell within the preset range that comprises this first count value, this comparer was exported this compare result signal.
Embodiments of the invention also disclose a kind of time figure conversion method, comprise: use at least one first delay-level to postpone first input signal to produce first output signal; Use at least one second delay-level to postpone second input signal to produce second output signal; Count this first output signal to produce first count value; Count this second output signal to produce second count value; And relatively this first count value and this second count value to produce compare result signal; Wherein this first delay-level has bigger retardation than this second delay-level, and this first count value early begins to be counted than this second count value, and when this second count value falls within the preset range that comprises this first count value, export this compare result signal.
Description of drawings
Fig. 1 has illustrated the time-to-digital conversion circuit according to the first embodiment of the present invention.
Fig. 2 has illustrated time-to-digital conversion circuit according to a second embodiment of the present invention.
[main element label declaration]
100,200 time-to-digital conversion circuits
101 first delay circuits
103 second delay circuits
105 first counters
107 second counters
109 comparers
111 AND doors
113 OR doors
115,117,119 first delay-level
121 AND doors
123 OR doors
125,127,129 second delay-level
201 control circuits
Embodiment
In the middle of instructions and above-mentioned claim, used some vocabulary to censure specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This instructions and above-mentioned claim are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be open term mentioned " comprising " in the middle of instructions and the above-mentioned request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " coupling " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other device or connection means if describe first device in the literary composition.
Fig. 1 has illustrated the time-to-digital conversion circuit 100 according to the first embodiment of the present invention.As shown in Figure 1, time-to-digital conversion circuit 100 comprises first delay circuit 101, second delay circuit 103, first counter 105, second counter 107 and comparer 109.First delay circuit 101 has at least one first delay-level 115,117,119, in order to postpone the first input signal In
1To produce the first output signal Out
1 Second delay circuit 103 has at least one second delay-level 125,127,129, in order to postpone the second input signal In
2(being known reference signal in this example) is to produce the second output signal Out
2Comparer 109 couples first counter 105 and second counter 107, in order to compare the first count value CV
1With the second count value CV
2To produce compare result signal CR.
Wherein first delay-level, 115,117,119 to the second delay-level 125,127,129 have bigger retardation, and first counter 105 early begins counting that is the first input signal In than second counter 107
1Than the second input signal In
2Early be transfused to.In this embodiment, as the first count value CV
1With the second count value CV
2When equating, promptly can be considered the second input signal In
2Caught up with the first input signal In
1, comparer 109 can output compare result signal CR then.In one embodiment, comparer 109 can be external to predetermining circuit and compare result signal CR and uses as the trigger pip of predetermining circuit.Yet, as the first count value CV
1With the second count value CV
2Be not equal, and its gap is when only being small gap, also can ignores this gap and the second input signal In
2Be considered as catching up with the first input signal In
1, such variation also belongs to scope of the present invention.That is, as the second count value CV
2Fall within and comprise the first count value CV
1Preset range in the time, with the second input signal In
2Be considered as catching up with the first input signal In
1And comparer 109 output compare result signal CR.
In addition, first delay circuit 101 in this embodiment also comprises AND door 111 and OR door 113.Wherein AND door 111 receives reset signal RES, in order to the first output signal Out that resets
1, and OR door 113 is coupled to AND door 111, in order to the output and the first input signal In according to AND door 111
1Output signal to first delay-level 115,117,119.Second delay circuit 103 also has AND door 121, OR door 123, second delay-level 125,127,129, and its structure is also identical with first delay circuit 101.Because first delay circuit 101 shown in Figure 1 and the detail operations mode of second delay circuit 103 are well known to those skilled in the art, so do not repeat them here.It is noted that first delay circuit 101 shown in Figure 1 and the structure of second delay circuit 103 are only in order to give an example the also applicable the present invention of the delay circuit of other structure.
According to the above embodiments, owing to be by the first count value CV
1With the second count value CV
2Judge the first input signal In
1Whether catch up with the second input signal In
2, and the first count value CV
1With the second count value CV
2Each count value is all represented more than one delay-level, therefore can save the area of delay circuit.For instance, if the first input signal In
1With the second input signal In
2Gap be n (t
s-t
f), then the delay circuit in known technology just needs n delay-level at least.But the cyclic delay circuit of time-to-digital conversion circuit is if having K delay-level according to an embodiment of the invention, and then each count value is just represented K (t
s-t
r), therefore just can
The delay circuit of times area is calculated identical gap.
Fig. 2 has illustrated time-to-digital conversion circuit 200 according to a second embodiment of the present invention.The element of embodiment shown in Figure 2 is similar with the framework of embodiment shown in Figure 1, and difference has been more than second embodiment shown in Figure 2 what delay-level control circuit 201 will produce output signal with to control first delay circuit 101 and second delay circuit 103.Therefore, the first output signal Out
1With the second output signal Out
2Can only corresponding first delay circuit 101 and second delay circuit 103 in the part delay-level, so can make the application of time-to-digital conversion circuit provided by the present invention more extensive.And, not necessarily will have control circuit 201 will produce output signal with what delay-level to select first delay circuit 101 and second delay circuit 103, those skilled in the art are when using other machine-processed control circuit 201 to select first delay circuit 101 and second delay circuit 103 to produce output signal with what delay-level.
Disclose according to an embodiment of the invention and also can obtain corresponding time figure conversion method, can be summarized as follows: use at least one first delay-level to postpone first input signal to produce first output signal; Use at least one second delay-level to postpone second input signal to produce second output signal; Count first output signal to produce first count value.Count second output signal to produce second count value; Relatively first count value and second count value are to produce compare result signal.
Other technical characterictic of the method can push away easily by above-listed description, so do not repeat them here.
The above only is embodiments of the invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. time-to-digital conversion circuit comprises:
First delay circuit has at least one first delay-level, in order to postpone first input signal to produce first output signal;
Second delay circuit has at least one second delay-level, in order to postpone second input signal to produce second output signal;
First counter couples this first delay circuit, in order to count this first output signal to produce first count value;
Second counter couples this second delay circuit, in order to count this second output signal to produce second count value; And
Comparer couples this first counter and this second counter, in order to relatively this first count value and this second count value to produce compare result signal;
Wherein this first delay-level has bigger retardation than this second delay-level, and this first counter early begins counting than this second counter, and when this second count value fell within the preset range that comprises this first count value, this comparer was exported this compare result signal.
2. time-to-digital conversion circuit according to claim 1, wherein this comparer is to export this compare result signal when this second count value equals this first count value.
3. time-to-digital conversion circuit according to claim 1, wherein this comparer is coupled to predetermining circuit, and this compare result signal is to use as the trigger pip of this predetermining circuit.
4. time-to-digital conversion circuit according to claim 1, wherein this first delay circuit has a plurality of first delay-level, and this first output signal is a part that corresponds in those first delay-level.
5. time-to-digital conversion circuit according to claim 1, wherein this second delay circuit has a plurality of second delay-level, and this second output signal is a part that corresponds in those second delay-level.
6. time figure conversion method comprises:
Use at least one first delay-level to postpone first input signal to produce first output signal;
Use at least one second delay-level to postpone second input signal to produce second output signal;
Count this first output signal to produce first count value;
Count this second output signal to produce second count value; And
Relatively this first count value and this second count value are to produce compare result signal;
Wherein this first delay-level has bigger retardation than this second delay-level, and this first count value early begins to be counted than this second count value, and when this second count value falls within the preset range that comprises this first count value, export this compare result signal.
7. time figure conversion method according to claim 6, wherein this relatively this first count value and this second count value are to export this compare result signal when this second count value equals this first count value in fact with the step that produces compare result signal.
8. time figure conversion method according to claim 6, wherein this compare result signal is to use as the trigger pip of predetermining circuit.
9. time figure conversion method according to claim 6, wherein at least one first delay-level of this use postpones first input signal and is to use a plurality of first delay-level with the step that produces first output signal, and this first output signal is a part that corresponds in those first delay-level.
10. time figure conversion method according to claim 6, wherein at least one second delay-level of this use postpones second input signal and is to use a plurality of second delay-level with this step that produces second output signal, and this second output signal is a part that corresponds in those second delay-level.
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| CN2008100807848A CN101515155B (en) | 2008-02-18 | 2008-02-18 | Time-to-digital conversion circuit and correlation method thereof |
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| CN101515155B true CN101515155B (en) | 2010-10-13 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355267B (en) * | 2011-05-30 | 2013-09-18 | 山东寿光科迪电子有限公司 | Cursor delay chain based time-digital conversion method and circuit thereof |
| JP5920564B2 (en) * | 2011-12-05 | 2016-05-18 | セイコーエプソン株式会社 | Timer device and electronic device |
| US8957712B2 (en) * | 2013-03-15 | 2015-02-17 | Qualcomm Incorporated | Mixed signal TDC with embedded T2V ADC |
| CN103257569B (en) * | 2013-05-23 | 2015-10-21 | 龙芯中科技术有限公司 | Time measuring circuit, method and system |
| CN104199276B (en) * | 2014-09-23 | 2017-01-11 | 李亚锋 | FPGA-based (field programmable gate array based) signal time difference measurement method and FPGA-based time-to-digital converter |
| DE102016222136A1 (en) | 2016-11-11 | 2018-05-17 | Robert Bosch Gmbh | Time-to-digital conversion device, LiDAR system and device |
| CN107193205B (en) * | 2017-05-24 | 2019-05-14 | 哈尔滨工业大学 | A kind of time memory circuit for pipeline-type time-to-digit converter |
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| US4879700A (en) * | 1987-05-04 | 1989-11-07 | Ball Corporation | Method and apparatus for determining the time between two signals |
| EP0357822A1 (en) * | 1988-09-08 | 1990-03-14 | Helmut K. Pinsch GmbH & Co. | Method and apparatus for measuring the time difference between pulses |
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| CN1696845A (en) * | 2005-05-13 | 2005-11-16 | 清华大学 | Method and device for measuring time interval through delay line in cascaded two stages |
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| EP0113935A2 (en) * | 1982-12-22 | 1984-07-25 | Philips Electronics Uk Limited | Timer circuit |
| US4879700A (en) * | 1987-05-04 | 1989-11-07 | Ball Corporation | Method and apparatus for determining the time between two signals |
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| EP0357822A1 (en) * | 1988-09-08 | 1990-03-14 | Helmut K. Pinsch GmbH & Co. | Method and apparatus for measuring the time difference between pulses |
| CN1696845A (en) * | 2005-05-13 | 2005-11-16 | 清华大学 | Method and device for measuring time interval through delay line in cascaded two stages |
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