CN107193205B - A kind of time memory circuit for pipeline-type time-to-digit converter - Google Patents
A kind of time memory circuit for pipeline-type time-to-digit converter Download PDFInfo
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- CN107193205B CN107193205B CN201710374780.XA CN201710374780A CN107193205B CN 107193205 B CN107193205 B CN 107193205B CN 201710374780 A CN201710374780 A CN 201710374780A CN 107193205 B CN107193205 B CN 107193205B
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
A kind of time storage circuit for pipeline-type time-to-digit converter, belongs to time fields of measurement, in order to solve the problems, such as that existing time memory can not handle the lesser input signal of time interval.Three input signals of impulse generator of the invention are respectively Start, Stop and Initial after two delay units, output end is as two inputs or first input terminal of door, Trigger is as two inputs or second input signal of door, control voltage end of the output signal end as grid-control time delay chain of two inputs or door；Two No. two delay units are respectively as follows: No. two delay unit A and No. two delay unit B；The input signal of No. two delay unit A is SET signal；No. two delay unit A are connected with No. two delay unit B；16 No. three delay units are cascaded, and the input terminal after series connection connects the output end of No. two delay unit B；Output end after series connection is the output end of the time memory circuit.It has the beneficial effect that and has handled the lesser input signal of time interval.
Description
Technical field
The invention belongs to time fields of measurement.
Background technique
High-resolution time-to-digit converter has important in high-energy physics, the fields such as laser ranging and accurate measurement
Application.Pipeline-type time-to-digit converter as high resolution time digital quantizer a kind of important implementation by
Extensive concern, time memory are the important components of pipeline-type time-to-digit converter, and performance directly determines
The function and precision of time-to-digit converter, therefore design and optimization important in inhibiting for time memory.
Existing time memory can not generate corresponding pulse when input signal time interval is smaller, to limit
The range of time measurement, while when quantization surplus is smaller, late-class circuit can not generate correct input signal, to make the time
Digital quantizer can not generate correct quantized result in this case, therefore, solve the problems, such as this pair of time memory
The function of perfect pipeline type time-to-digit converter simultaneously improves its performance and is of great significance.
Summary of the invention
The lesser input signal of time interval can not be handled the purpose of the present invention is to solve existing time memory to ask
Topic, proposes a kind of time storage circuit for pipeline-type time-to-digit converter.
A kind of time memory circuit for pipeline-type time-to-digit converter of the present invention, including pulse hair
Raw device, two inputs or door, two No.1 delay units and grid-control time delay chain；
Input signal Start and input signal Stop is two rising edges, and input signal Initial is initial signal；
First input signal of the input signal Start as impulse generator, input signal Stop is by two delays
As second input signal of impulse generator after unit, input signal Initial is defeated as the third of impulse generator
Enter signal；
Two input of output end connection of impulse generator or first input terminal of door, two inputs or second input of door
The control voltage end of the output signal end connection grid-control time delay chain of end reception input signal Trigger, two inputs or door；
Grid-control time delay chain includes two No. two delay units and 16 No. three delay units；
The output signal end of two inputs or door simultaneously with the control voltage end of two No. two delay units and 16 No. three
The control voltage end of delay unit is connected；
Two No. two delay units are respectively as follows: No. two delay unit A and No. two delay unit B；No. two delay unit A's is defeated
Entering signal is SET signal；The output end of No. two delay unit A is connected with the input terminal of No. two delay unit B；
16 No. three delay units are cascaded, and the input terminal after series connection connects the output end of No. two delay unit B；
Output end after series connection is the output end for being used for the time memory circuit of pipeline-type time-to-digit converter.
The operation principle of the present invention is that: impulse generator by input signal Start with by delay after input signal
Time interval between Stop is converted to pulse signal, and input signal Initial is initial signal, and pulse width is input signal
The time interval of Start and input signal Stop add the sum of the delay of two No.1 delay units, the pulse signal with
Trigger signal is by two inputs or behind the door as the control signal EN of grid-control time delay chain, when controlling signal EN is high level,
SET signal is propagated in time delay chain, and when control signal EN signal is low level, the spread state of SET signal is kept, and is being controlled
Signal EN processed continues to propagate when next high level arrives, introduced in grid-control time delay chain two No. two additional delay units with
The error for being delayed and being introduced to input signal Stop is eliminated, definition output is the last one No. three delays in grid-control time delay chain
Time difference between the output of unit and Trigger signal then includes the time interval of input signal in output signal, thus real
The storage of time is showed.
The beneficial effects of the invention are as follows by carrying out certain delay to input signal Stop, it is ensured that impulse generator exists
Input signal time interval still is able to output pulse signal when smaller, while increasing additional two two in grid-control time delay chain
Number delay unit eliminates the error introduced due to being delayed to input signal Stop, thus guaranteeing time memory function
Its measurement range is expanded on the basis of energy is correct；The present invention is for may insure the same level in pipeline-type time-to-digit converter
When the quantization surplus that circuit generates is smaller, junior's circuit still is able to generate correct input signal, while can make time number
Word converter measures lesser time interval, improves its dynamic range.
Detailed description of the invention
Fig. 1 is that a kind of time storage for pipeline-type time-to-digit converter described in embodiment one is embodied
The circuit diagram of device circuit；
Fig. 2 is a kind of time memory circuit for pipeline-type time-to-digit converter in specific embodiment one
Operation principle schematic diagram；
Fig. 3 is the circuit diagram for the impulse generator being embodied in two；
Fig. 4 is the circuit diagram of the first trigger in specific embodiment three.
Specific embodiment
Specific embodiment 1: illustrating present embodiment in conjunction with Fig. 1 and Fig. 2, one kind described in present embodiment is for flowing
The time memory circuit of pipeline type time-to-digit converter, including 2, two No.1 delays of the input of impulse generator 1, two or door
Unit 3 and grid-control time delay chain 4；
Input signal Start and input signal Stop is two rising edges, and input signal Initial is initial signal；
First input signal of the input signal Start as impulse generator 1, input signal Stop is by two delays
As second input signal of impulse generator 1, third of the input signal Initial as impulse generator 1 after unit 3
Input signal；
Second of two input of output end connection of impulse generator 1 or first input terminal of door 2, two inputs or door 2
The control voltage end of the output signal end connection grid-control time delay chain 4 of input terminal reception input signal Trigger, two inputs or door 2；
Grid-control time delay chain 4 includes two No. two delay units and 16 No. three delay units；
The output signal end of two inputs or door 2 simultaneously with the control voltage end of two No. two delay units and 16 No. three
The control voltage end of delay unit is connected；
Two No. two delay units are respectively as follows: No. two delay unit A and No. two delay unit B；No. two delay unit A's is defeated
Entering signal is SET signal；The output end of No. two delay unit A is connected with the input terminal of No. two delay unit B；
16 No. three delay units are cascaded, and the input terminal after series connection connects the output end of No. two delay unit B；
Output end after series connection is the output end for being used for the time memory circuit of pipeline-type time-to-digit converter.
In the present embodiment, 1. 16 No. three delay units are respectively as follows: No. three delay units to No. three delay units16 No. three delay units are cascaded, also, the output end of No. two delay unit B and No. three delay units are 1.
Input terminal is connected；No. three delay unitsOutput end be this be used for pipeline-type time-to-digit converter time memory
The output end of circuit.
Illustrate the working principle of present embodiment referring to Fig. 2, input signal Start and input signal Stop are two risings
Edge, time interval Tin, since input signal Stop signal passes through the delay of two No.1 delay units 3, so pulse is sent out
The pulse width that raw device 1 exports is Tin+2τp, the pulse signal and input signal Trigger that impulse generator 1 issues are by two
Control signal EN after input or door 2 as grid-control time delay chain 4, in pulse width Tin+2τpInterior, SET signal will propagate Tin+2
τp；When controlling signal EN signal is low level, spread state is kept, when the high level of input signal Trigger arrives,
SET signal continues to propagate, in order to eliminate due to increasing in grid-control time delay chain 4 to error caused by input signal Stop delay
Add two No. two additional delay units, when SET signal propagates to the last one No. three delay unit 16 of grid-control time delay chain 4
When, if the output signal of No. three delay units 16 is Full signal, then Full signal delay time is TFS+2τp, wherein TFSFor
The maximum delay of grid-control time delay chain 4 when not increasing additional delay unit defines output signal ToutFor the last of grid-control time delay chain 4
Time interval between the output signal and input signal Trigger rising edge of one No. three delay unit 16, then ToutIt can be with table
It is shown as:
Tout=(TFS+2τp)-(Tin+2τp)=TFS-Tin；
Time interval between the output signal and input signal Trigger rising edge of the last one No. three delay unit 16
The time interval between input signal Start and input signal Stop is contained, to realize the storage of time.
Specific embodiment 2: embodiment is described with reference to Fig. 3, present embodiment is to described in specific embodiment one
A kind of time memory circuit for pipeline-type time-to-digit converter further limit, in the present embodiment, institute
Stating impulse generator 1 includes the first trigger 101, the second trigger 102 and No.1 phase inverter 103；
Clock end input signal of the input signal Start as the first trigger 101, the D input terminal of the first trigger 101
Connect high level；
Clock end input signal of the input signal Stop as the second trigger 102 after delay, the second trigger
102 D input termination high level；
The reset terminal Rst of first trigger 101 is connected with the reset terminal Rst of the second trigger 102；
The reset terminal Rstn of first trigger 101 is connected with the reset terminal Rstn of the second trigger 102；
The reset terminal RstA of first trigger 101 is connected with the reset terminal RstA of the second trigger 102；
The reset terminal RstB of first trigger 101 is connected with the reset terminal RstB of the second trigger 102；
Input signal Initial simultaneously with the input terminal of No.1 phase inverter 103, the reset terminal Rst of the first trigger 101 and
The reset terminal Rst of second trigger 102 is connected；
The output end of No.1 phase inverter 103 simultaneously with the reset terminal Rstn of the first trigger 101 and the second trigger 102
Reset terminal Rstn is connected；
The output end of second trigger 102 simultaneously with the reset terminal RstB of the first trigger 101 and the second trigger 102
Reset terminal RstB is connected；
The output end of first trigger 101 simultaneously with the reset terminal RstA of the first trigger 101 and the second trigger 102
Reset terminal RstA is connected, and using the output end of the first trigger 101 as the output end of impulse generator 1.
In the present embodiment, when input signal Initial is high level, the first trigger 101 and the second trigger
102 reset, and the output of the first trigger 101 and the output of the second trigger are low level；When input signal Initial is low
When level, reset terminal Rstn is high level at this time, and when input signal Start rising edge arrives, the first trigger 101 exports high electricity
Flat, reset terminal RstA is high level at this time, when the input signal Stop after delay arrives, the output of the second trigger 102
High level, reset terminal RstB is high level at this time, and the first trigger 101 and the second trigger 102 reset simultaneously, so the first touching
The pulse width that hair device 101 exports is input signal Initial and two rising edges of input signal Stop after delay
Between time interval.
Specific embodiment 3: embodiment is described with reference to Fig. 4, present embodiment is to described in specific embodiment two
A kind of time memory circuit for pipeline-type time-to-digit converter further limit, in the present embodiment,
One trigger 101 is identical with the structure of the second trigger 102, and the first trigger 101 and the second trigger 102 are D touching
Send out device；
First trigger 101 includes metal-oxide-semiconductor Q1-metal-oxide-semiconductor Q13, No. two phase inverters 104 and power vd D；
The anode of power vd D is connected with the source electrode of the source electrode of metal-oxide-semiconductor Q1, the source electrode of metal-oxide-semiconductor Q4 and metal-oxide-semiconductor Q11 simultaneously；
The source electrode of metal-oxide-semiconductor Q3, the source electrode of metal-oxide-semiconductor Q6, the source electrode of metal-oxide-semiconductor Q9, the source electrode of metal-oxide-semiconductor Q10 and metal-oxide-semiconductor Q13
Source electrode is grounded simultaneously；
The D input terminal of the grid of metal-oxide-semiconductor Q1 and the grid common node of metal-oxide-semiconductor Q3 as the first trigger 101；
The grid common node conduct of the grid of metal-oxide-semiconductor Q2, the grid of metal-oxide-semiconductor Q4, the grid of metal-oxide-semiconductor Q6 and metal-oxide-semiconductor Q12
The clock end of first trigger 101；
Reset terminal RstA of the grid of metal-oxide-semiconductor Q7 as the first trigger 101；
Reset terminal RstB of the grid of metal-oxide-semiconductor Q8 as the first trigger 101；
Reset terminal Rstn of the grid of metal-oxide-semiconductor Q9 as the first trigger 101；
Reset terminal Rst of the grid of metal-oxide-semiconductor Q10 as the first trigger 101；
The drain electrode of metal-oxide-semiconductor Q1 is connected with the source electrode of metal-oxide-semiconductor Q2；The drain electrode of metal-oxide-semiconductor Q2 and the drain electrode of metal-oxide-semiconductor Q3 simultaneously with
The grid of metal-oxide-semiconductor Q5 is connected；
The drain electrode of metal-oxide-semiconductor Q4, the drain electrode of metal-oxide-semiconductor Q5, the drain electrode of metal-oxide-semiconductor Q7, the drain electrode of metal-oxide-semiconductor Q10 and metal-oxide-semiconductor Q11
Grid is connected with the grid of metal-oxide-semiconductor Q13 simultaneously；
The source electrode of metal-oxide-semiconductor Q5 is connected with the drain electrode of metal-oxide-semiconductor Q6:
The source electrode of metal-oxide-semiconductor Q7 is connected with the drain electrode of metal-oxide-semiconductor Q8；
The source electrode of metal-oxide-semiconductor Q8 is connected with the drain electrode of metal-oxide-semiconductor Q9；
The source electrode of metal-oxide-semiconductor Q12 is connected with the drain electrode of metal-oxide-semiconductor Q13；
The drain electrode of metal-oxide-semiconductor Q11 and the drain electrode of metal-oxide-semiconductor Q12 are connected with the input terminal of No. two phase inverters 104 simultaneously；
The output end of No. two phase inverters 104 is the output end of the first trigger 101.
Specific embodiment 4: present embodiment is to one kind described in specific embodiment three for the pipeline-type time
The time memory circuit of digital quantizer further limits, in the present embodiment, metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q4 and
Metal-oxide-semiconductor Q11 is PMOS tube；
Metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6, metal-oxide-semiconductor Q7, metal-oxide-semiconductor Q8, metal-oxide-semiconductor Q9, metal-oxide-semiconductor Q10, metal-oxide-semiconductor Q12 and
Metal-oxide-semiconductor Q13 is NMOS tube.
Specific embodiment 5: present embodiment is to one kind described in specific embodiment one for the pipeline-type time
The time memory circuit of digital quantizer further limits, and in the present embodiment, No. two delay unit A, No. two delays are single
First B and two No.1 delay unit 3 is identical.
In the present embodiment, two No.1 delay units 3 are eliminated by No. two delay unit A and No. two delay unit B
To input signal Stop be delayed caused by error.
Claims (4)
1. a kind of time memory circuit for pipeline-type time-to-digit converter, which is characterized in that including pulse generation
Device (1), two inputs or door (2), two No.1 delay units (3) and grid-control time delay chain (4)；
Input signal Start and input signal Stop is two rising edges, and input signal Initial is initial signal；
First input signal of the input signal Start as impulse generator (1), input signal Stop are single by two delays
First (3) afterwards as second input signal of impulse generator (1), input signal Initial as impulse generator (1) the
Three input signals；
The second of two input of output end connection of impulse generator (1) or first input terminal of door (2), two inputs or door (2)
A input terminal receives the control of input signal Trigger, two inputs or output signal end connection grid-control time delay chain (4) of door (2)
Voltage end；
Grid-control time delay chain (4) includes two No. two delay units and 16 No. three delay units；
The output signal end of two inputs or door (2) prolongs with the control voltage end of two No. two delay units and 16 No. three simultaneously
The control voltage end of Shi Danyuan is connected；
Two No. two delay units are respectively as follows: No. two delay unit A and No. two delay unit B；The input letter of No. two delay unit A
Number be SET signal；The output end of No. two delay unit A is connected with the input terminal of No. two delay unit B；
16 No. three delay units are cascaded, and the input terminal after series connection connects the output end of No. two delay unit B；Series connection
Output end afterwards is the output end for being used for the time memory circuit of pipeline-type time-to-digit converter.
2. a kind of time memory circuit for pipeline-type time-to-digit converter according to claim 1, special
Sign is that the impulse generator (1) includes the first trigger (101), the second trigger (102) and No.1 phase inverter (103)；
Clock end input signal of the input signal Start as the first trigger (101), the D input terminal of the first trigger (101)
Connect high level；
Clock end input signal of the input signal Stop as the second trigger (102) after delay, the second trigger
(102) D input termination high level；
The reset terminal Rst of first trigger (101) is connected with the reset terminal Rst of the second trigger (102)；
The reset terminal Rstn of first trigger (101) is connected with the reset terminal Rstn of the second trigger (102)；
The reset terminal RstA of first trigger (101) is connected with the reset terminal RstA of the second trigger (102)；
The reset terminal RstB of first trigger (101) is connected with the reset terminal RstB of the second trigger (102)；
Input signal Initial simultaneously with the input terminal of No.1 phase inverter (103), the reset terminal Rst of the first trigger (101) and
The reset terminal Rst of second trigger (102) is connected；
The output end of No.1 phase inverter (103) the reset terminal Rstn and the second trigger (102) with the first trigger (101) simultaneously
Reset terminal Rstn be connected；
The output end of second trigger (102) the reset terminal RstB and the second trigger (102) with the first trigger (101) simultaneously
Reset terminal RstB be connected；
The output end of first trigger (101) the reset terminal RstA and the second trigger (102) with the first trigger (101) simultaneously
Reset terminal RstA be connected, and using the output end of the first trigger (101) as the output end of impulse generator (1).
3. a kind of time memory circuit for pipeline-type time-to-digit converter according to claim 2, special
Sign is that the first trigger (101) is identical with the structure of the second trigger (102), and the first trigger (101) and the second touching
Sending out device (102) is d type flip flop；
First trigger (101) includes metal-oxide-semiconductor Q1-metal-oxide-semiconductor Q13, No. two phase inverters (104) and power vd D；
The anode of power vd D is connected with the source electrode of the source electrode of metal-oxide-semiconductor Q1, the source electrode of metal-oxide-semiconductor Q4 and metal-oxide-semiconductor Q11 simultaneously；
The source electrode of metal-oxide-semiconductor Q3, the source electrode of metal-oxide-semiconductor Q6, the source electrode of metal-oxide-semiconductor Q9, the source electrode of metal-oxide-semiconductor Q10 and metal-oxide-semiconductor Q13 source electrode
It is grounded simultaneously；
The D input terminal of the grid of metal-oxide-semiconductor Q1 and the grid common node of metal-oxide-semiconductor Q3 as the first trigger (101)；
The grid of metal-oxide-semiconductor Q2, the grid of metal-oxide-semiconductor Q4, metal-oxide-semiconductor Q6 grid and metal-oxide-semiconductor Q12 grid common node as first
The clock end of trigger (101)；
Reset terminal RstA of the grid of metal-oxide-semiconductor Q7 as the first trigger (101)；
Reset terminal RstB of the grid of metal-oxide-semiconductor Q8 as the first trigger (101)；
Reset terminal Rstn of the grid of metal-oxide-semiconductor Q9 as the first trigger (101)；
Reset terminal Rst of the grid of metal-oxide-semiconductor Q10 as the first trigger (101)；
The drain electrode of metal-oxide-semiconductor Q1 is connected with the source electrode of metal-oxide-semiconductor Q2；The drain electrode of metal-oxide-semiconductor Q2 and the drain electrode of metal-oxide-semiconductor Q3 while and metal-oxide-semiconductor
The grid of Q5 is connected；
The grid of the drain electrode of metal-oxide-semiconductor Q4, the drain electrode of metal-oxide-semiconductor Q5, the drain electrode of metal-oxide-semiconductor Q7, the drain electrode of metal-oxide-semiconductor Q10 and metal-oxide-semiconductor Q11
It is connected simultaneously with the grid of metal-oxide-semiconductor Q13；
The source electrode of metal-oxide-semiconductor Q5 is connected with the drain electrode of metal-oxide-semiconductor Q6:
The source electrode of metal-oxide-semiconductor Q7 is connected with the drain electrode of metal-oxide-semiconductor Q8；
The source electrode of metal-oxide-semiconductor Q8 is connected with the drain electrode of metal-oxide-semiconductor Q9；
The source electrode of metal-oxide-semiconductor Q12 is connected with the drain electrode of metal-oxide-semiconductor Q13；
The drain electrode of metal-oxide-semiconductor Q11 and the drain electrode of metal-oxide-semiconductor Q12 are connected with the input terminal of No. two phase inverters (104) simultaneously；
The output end of No. two phase inverters (104) is the output end of the first trigger (101)；
Metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q4 and metal-oxide-semiconductor Q11 are PMOS tube；
Metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6, metal-oxide-semiconductor Q7, metal-oxide-semiconductor Q8, metal-oxide-semiconductor Q9, metal-oxide-semiconductor Q10, metal-oxide-semiconductor Q12 and metal-oxide-semiconductor
Q13 is NMOS tube.
4. a kind of time memory circuit for pipeline-type time-to-digit converter according to claim 1, special
Sign is that No. two delay unit A, No. two delay unit B and two No.1 delay units (3) are identical.
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| CN101515155B (en) * | 2008-02-18 | 2010-10-13 | 瑞昱半导体股份有限公司 | Time-to-digital conversion circuit and correlation method thereof |
| US8222607B2 (en) * | 2010-10-29 | 2012-07-17 | Kabushiki Kaisha Toshiba | Apparatus for time to digital conversion |
| US9250612B2 (en) * | 2014-03-18 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for a time-to-digital converter |
| US9223295B2 (en) * | 2014-04-18 | 2015-12-29 | International Business Machines Corporation | Time-to-digital converter |
| CN106019923B (en) * | 2016-05-18 | 2018-11-13 | 中国科学技术大学 | A kind of time-digital converter based on FPGA |
| CN106200356B (en) * | 2016-09-23 | 2019-01-25 | 中国科学院上海高等研究院 | Vernier annular time-to-digit converter |
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