CN111313870A - Narrow pulse precision time delay synchronization method and device based on phase compensation - Google Patents
Narrow pulse precision time delay synchronization method and device based on phase compensation Download PDFInfo
- Publication number
- CN111313870A CN111313870A CN201911128266.3A CN201911128266A CN111313870A CN 111313870 A CN111313870 A CN 111313870A CN 201911128266 A CN201911128266 A CN 201911128266A CN 111313870 A CN111313870 A CN 111313870A
- Authority
- CN
- China
- Prior art keywords
- pulse
- clock
- control unit
- synchronous
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
Abstract
The invention discloses a narrow pulse precise time delay synchronization method and device based on phase compensation, and relates to the technical fields of precision machining, medical treatment, scientific research and the like. The method comprises the following steps: processing the input narrow pulse signal to obtain a synchronous control signal and a pulse synchronous clock; inputting a local clock and a pulse synchronous clock into a clock generator to generate a pulse following output clock and a local frequency multiplication output clock; inputting a local frequency multiplication output clock into IDELAY control, generating a pulse to follow the output clock, inputting the pulse to a carry chain, outputting the pulse to enter an internal IDELAY resource, and performing precise clock synchronization control on an input narrow pulse and the generated follow clock; the required output clock is generated by clock conversion by the synchronous clock generated above. And then, the FPGA internal resources are utilized to realize delay control of the output clock, pulse width control of the output clock and selective output of different clocks.
Description
Technical Field
The invention relates to the technical fields of precision machining, medical treatment, scientific research and the like, in particular to a laser pulse precision delay synchronous control method.
Background
In ultrafast phenomenon and large-scale precise physical experiments related to the fields of laser precise control, laser nuclear physics, plasma physics, electric discharge and the like, due to the influences of inherent time delay of each subsystem and slight difference of the lengths of signal transmission cables, multi-path trigger signals are delayed and cannot arrive synchronously. An important feature of such experimental research is that the time domain often has strict requirements on the trigger time of each path of signal, which requires a delay synchronization control device to make a pre-delay according to the inherent delay of each path of system before the trigger signal enters each path of system. The delay precision is the most important technical index of the delay synchronization mechanism, which requires precise synchronization control of the action timing sequence of each subsystem.
Generally, the implementation delay method is divided into two main categories, namely special purpose and general purpose. The special delay unit is realized by adopting an analog device, and has the characteristics of high delay precision which can reach 10ps grade, but small dynamic range (less than 50 ns); the general digital delay unit is generally realized by a programmable logic device, and a counter can realize a larger delay dynamic range, but has the defects of limitation of the working frequency of the device and lower precision (generally 5 ns). Meanwhile, the counter starts counting when the external trigger signal arrives, but the phase relation between the external trigger signal and the local clock is random, the maximum jitter value is close to 1 clock cycle, and the phase relation between the counting delay output and the clock is determined, so that the delay output and the external trigger signal have large jitter. Moreover, the input signal has a certain time delay after being processed by the logic circuit, so that the time delay of the external trigger signal and the output signal is larger.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a narrow pulse precision time delay synchronization method and a device based on phase compensation. According to the method, a narrow pulse control unit is used for carrying out synchronous signal control on a narrow pulse, a PLL is used for generating a synchronous clock, and then IDELAY and a carry chain are used for carrying out precise synchronous control on an input pulse and the generated clock. The control of pulse delay output and pulse width is realized through the delay synchronous pulse control unit. All the designs of the invention are integrated in one FPGA, the circuit is simple and reliable, the integration level is high, and the power consumption is low.
In order to achieve the above object, the present invention provides a method and an apparatus for synchronizing a narrow pulse precision time delay based on phase compensation.
A narrow pulse precise time delay synchronization method based on phase compensation is realized in an FPGA (field programmable gate array), and comprises the steps of processing an input narrow pulse signal to obtain a synchronization control signal and a pulse synchronization control clock;
generating a pulse following output clock and a local frequency multiplication output clock by inputting a local clock and a pulse synchronous clock into a clock generator;
the method is characterized in that a local frequency multiplication output clock is adopted to input IDELAY control, generated pulses are input into a carry chain along with the output clock, and then the generated pulses are output into an internal IDELAY resource for carrying out precise clock synchronization control on the input narrow pulses and the generated follow clock.
Performing clock conversion through the generated synchronous clock to generate a required output clock; in addition, the delay chain realized by using the internal resources of the FPGA is used for carrying out delay control on the output clock, the pulse width chain realized by using the internal resources of the FPGA is used for realizing pulse width control on the output clock, and different clock selection outputs are realized through different IO interfaces of the FPGA; setting a frequency setting value, a time delay setting value and a pulse width setting value through corresponding registers respectively;
and generating a communication bus through FPGA internal resources to realize the configuration of the register, thereby generating various required delay synchronous clocks.
Optionally, the clock generator is a PLL, which is internally set to minimum output Jitter mode.
In addition, according to the method for the precise time delay synchronization, the invention also provides a narrow pulse precise time delay synchronization device based on phase compensation; the device comprises:
the narrow pulse control unit is used for reporting a synchronous signal to the input narrow pulse;
the clock generator is used for carrying out follow-up output and local clock frequency multiplication output on the narrow pulse clock;
an input synchronization control unit for performing a fine clock synchronization control of an input pulse and a generated clock;
the delay synchronous pulse control unit is used for generating clocks with different frequencies, different output delays and different pulse widths;
a pulse output control unit for selecting different pulse outputs;
a frequency control unit for setting a frequency value;
a Td control unit for setting a delay value; and the number of the first and second groups,
a Tw control unit for setting a pulse width value;
the frequency control unit, the Td control unit and the Tw control unit are respectively electrically connected with the delay synchronous pulse control unit;
the input synchronous control unit consists of an IDELAY and a carry chain;
the delay synchronous pulse control unit consists of a clock converter, a delay chain and a counting chain;
the narrow pulse control unit, the input synchronous control unit, the delay synchronous control unit and the pulse output control unit are electrically connected in sequence; the narrow pulse control unit, the clock generator and the input synchronous control unit are electrically connected in sequence; the frequency control unit, the Td control unit, and the Tw control unit are electrically connected to the control information input unit, respectively.
Optionally, the apparatus further includes a control information input unit that controls the frequency control unit, the Td control unit, and the Tw control unit.
Optionally, the reporting of the synchronization signal of the narrow pulse control unit includes a pulse triggering, multiple phase trigger triggering and sampling, and ADC sampling synchronization reporting mode.
Optionally, the clock generator further comprises a crystal oscillator of which the local clock input by the PLL is high precision, and the PLL is equal to or greater than one.
Optionally, the clock generator further comprises a PLL that inputs a local clock that is a high-precision 200M LVDS differential clock and outputs a clock that is 500M.
Optionally, the frequency control unit, the Td control unit, the Tw control unit, and the pulse output control unit further include, but are not limited to, delay pulse information control of a single channel, and may control multi-channel pulse setting information.
Optionally, the pulse output control unit further includes an output pulse for selecting a laser pulse, which may be a pulse with the same frequency or a pulse with a frequency reduced.
Optionally, the delay synchronization pulse control unit further includes a clock conversion unit, a delay chain, and a pulse width chain. The delay chain comprises an IDELAY chain, a carry chain, a trigger chain and a delay chain realized in a counting chain mode.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention synchronously controls and follows the input narrow pulse, utilizes the internal resources of the FPGA to realize the control of the delay, the pulse width and the frequency of the output pulse, and achieves the purpose of various scene applications. All designs are integrated in one FPGA, and the circuit is simple and reliable, high in integration level and low in power consumption.
Drawings
Fig. 1 is a schematic block diagram of the narrow pulse precision time delay synchronization of the present invention.
Fig. 2 is a schematic structural diagram of a narrow pulse precision time delay synchronization device according to the present invention.
FIG. 3 is a block diagram of a carry chain logic circuit design according to the present invention.
Fig. 4 is a timing diagram of the multi-stage link delay of the present invention.
Detailed Description
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
The above and further features and advantages of the present invention will be apparent from the following, complete description of the invention, taken in conjunction with the accompanying drawings, wherein the described embodiments are merely some, but not all embodiments of the invention.
In order to overcome the defects of the prior art, the invention provides a narrow pulse precision time delay synchronization method and a device based on phase compensation. The narrow pulse is subjected to synchronous signal control by a narrow pulse control unit, a PLL is additionally utilized to generate a synchronous clock, and then IDELAY and a carry chain are adopted to perform precise synchronous control on the input pulse and the generated clock. The control of pulse delay output and pulse width is realized through the delay synchronous pulse control unit. All the designs of the invention are integrated in one FPGA, the circuit is simple and reliable, the integration level is high, and the power consumption is low.
A narrow pulse precise time delay synchronization method based on phase compensation is realized in an FPGA (field programmable gate array), and comprises the steps of processing an input narrow pulse signal to obtain a synchronization control signal and a pulse synchronization control clock;
generating a pulse following output clock and a local frequency multiplication output clock by inputting a local clock and a pulse synchronous clock into a clock generator;
the method is characterized in that a local frequency multiplication output clock is adopted to input IDELAY control, generated pulses are input into a carry chain along with the output clock, and then the generated pulses are output into an internal IDELAY resource for carrying out precise clock synchronization control on the input narrow pulses and the generated follow clock.
Performing clock conversion through the generated synchronous clock to generate a required output clock; in addition, the delay chain realized by using the internal resources of the FPGA is used for carrying out delay control on the output clock, the pulse width chain realized by using the internal resources of the FPGA is used for realizing pulse width control on the output clock, and different clock selection outputs are realized through different IO interfaces of the FPGA; setting a frequency setting value, a time delay setting value and a pulse width setting value through corresponding registers respectively;
and generating a communication bus through FPGA internal resources to realize the configuration of the register, thereby generating various required delay synchronous clocks.
The clock generator is a PLL that is internally set to a minimum output Jitter mode.
In addition, according to the method for the precise time delay synchronization, the invention also provides a narrow pulse precise time delay synchronization device based on phase compensation; the device comprises:
the narrow pulse control unit is used for reporting a synchronous signal to the input narrow pulse;
the clock generator is used for carrying out follow-up output and local clock frequency multiplication output on the narrow pulse clock;
an input synchronization control unit for performing a fine clock synchronization control of an input pulse and a generated clock;
the delay synchronous pulse control unit is used for generating clocks with different frequencies, different output delays and different pulse widths;
a pulse output control unit for selecting different pulse outputs;
a frequency control unit for setting a frequency value;
a Td control unit for setting a delay value; and the number of the first and second groups,
a Tw control unit for setting a pulse width value;
the frequency control unit, the Td control unit and the Tw control unit are respectively electrically connected with the delay synchronous pulse control unit;
the input synchronous control unit consists of an IDELAY and a carry chain;
the delay synchronous pulse control unit consists of a clock converter, a delay chain and a counting chain;
the narrow pulse control unit, the input synchronous control unit, the delay synchronous control unit and the pulse output control unit are electrically connected in sequence; the narrow pulse control unit, the clock generator and the input synchronous control unit are electrically connected in sequence; the frequency control unit, the Td control unit, and the Tw control unit are electrically connected to the control information input unit, respectively.
The apparatus further includes a control information input unit which controls the frequency control unit, the Td control unit, and the Tw control unit.
The narrow pulse control unit reports the synchronous signals in a pulse triggering, multi-phase trigger triggering sampling and ADC sampling synchronous reporting mode.
The clock generator also comprises a crystal oscillator with high precision, wherein the local clock input by the PLL is more than or equal to one.
The clock generator also includes a PLL input with a local clock of high precision 200M LVDS differential clock and an output clock of 500M.
The frequency control unit, the Td control unit, the Tw control unit and the pulse output control unit also comprise but are not limited to single-channel delay pulse information control, and can control multi-channel pulse setting information.
The pulse output control unit also comprises an output pulse for selecting laser pulses, which can be pulses with the same frequency or pulses subjected to frequency reduction.
The delay synchronous pulse control unit also comprises a clock conversion unit, a delay chain and a pulse width chain; the delay chain comprises an IDELAY chain, a carry chain, a trigger chain and a delay chain realized in a counting chain mode.
As shown in fig. 1, a schematic block diagram of a narrow pulse precision time delay synchronization based on phase compensation. The system carries out synchronous signal control on the narrow pulse through a narrow pulse control unit, in addition, a PLL is utilized to generate a synchronous clock, and then IDELAY and a carry chain are adopted to carry out precise synchronous control on the input pulse and the generated clock. The control of pulse delay output and pulse width is realized through the delay synchronous pulse control unit. And finally, the control output of the pulse is realized through the pulse output control unit.
Fig. 2 is a schematic structural diagram of a narrow-pulse precision time delay synchronizer. A specific implementation method of the device is as follows: the device comprises a pulse control unit PLUSE _ CTRL, a phase-locked loop PLL, a synchronization control unit SYNC _ CTRL, a DELAY pulse synchronization control unit DELAY _ SYNC _ CTRL, a pulse output selection MUX, a Td \ Tw control unit Td \ Tw CTRL unit and a serial port UART. All modules are realized by using the internal logic resources of the FPGA. The synchronous control of pulse input signals is realized by utilizing a PLL and a logic circuit, the input differential signals are LVDS interfaces, and the clock frequency is 200M. Secondly, the precise compensation of the link delay is realized by utilizing internal IDELAY [1: N ] and CARRY4[1: N ] resources, wherein N is more than or equal to 1 and is determined according to the specific implementation situation. In addition, CLK SWITCH [1: N ] is used to realize different output pulse conversion, where N is equal to or greater than 1, and is determined according to the number of interfaces required to be output; DELAY CHAIN [1: N ] is used to realize precise DELAY control, where N ≧ 1, depending on the particular implementation; PW CHAIN [1: N ] is used to achieve precise pulse width control, where N is 1 or more, depending on the particular implementation. And finally, realizing the selection control of pulse output through MUX resources.
FIG. 3 is a block diagram of the carry chain logic circuit design. A plurality of CARRY units are used for link connection, and precise delay control is realized by utilizing a CARRY chain. Wherein N is more than or equal to 1, which is determined according to specific implementation conditions.
As shown in fig. 4, it is a timing diagram of the delay of the clock through different numbers of links. The larger the link passes through, the larger the time delay is, and the multiple of the time delay and the number of the links are in direct proportion.
The above-mentioned embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above-mentioned embodiments are only examples of the present invention and are not intended to limit the scope of the present invention. It should be understood that any modifications, equivalents, improvements and the like, which come within the spirit and principle of the invention, may occur to those skilled in the art and are intended to be included within the scope of the invention.
Claims (10)
1. A narrow pulse precise time delay synchronization method based on phase compensation is characterized in that the method is realized in an FPGA and comprises the following steps:
processing the input narrow pulse signal to obtain a synchronous control signal and a pulse synchronous clock;
generating a pulse following output clock and a local frequency multiplication output clock by inputting a local clock and a pulse synchronous clock into a clock generator;
inputting IDELAY control by adopting a local frequency multiplication output clock, generating a pulse to follow the output clock, inputting the pulse to a carry chain, outputting the pulse to enter an internal IDELAY resource, and performing precise clock synchronization control on an input narrow pulse and the generated follow clock;
performing clock conversion through the generated synchronous clock to generate a required output clock; in addition, clocks with different frequencies are generated through clock conversion realized by using FPGA internal resources, delay control is carried out on an output clock through a delay chain realized by using the FPGA internal resources, pulse width control on the output clock is realized through a pulse width chain realized by using the FPGA internal resources, and different clock selection outputs are realized through different IO interfaces of the FPGA; setting a frequency setting value, a time delay setting value and a pulse width setting value through corresponding registers respectively;
and generating a communication bus through FPGA internal resources to realize the configuration of the register, thereby generating various required delay synchronous clocks.
2. The method of claim 1, wherein the clock generator is a PLL internally set in a minimum output Jitter mode.
3. A narrow pulse precision time delay synchronizer based on phase compensation is characterized by comprising:
the narrow pulse control unit is used for reporting a synchronous signal to the input narrow pulse;
the clock generator is used for carrying out follow-up output and local clock frequency multiplication output on the narrow pulse clock;
an input synchronization control unit for performing a fine clock synchronization control of an input pulse and a generated clock;
the delay synchronous pulse control unit is used for generating clocks with different frequencies, different output delays and different pulse widths;
a pulse output control unit for selecting different pulse outputs;
a frequency control unit for setting a frequency value;
a Td control unit for setting a delay value; and the number of the first and second groups,
a Tw control unit for setting a pulse width value;
the frequency control unit, the Td control unit and the Tw control unit are respectively electrically connected with the delay synchronous pulse control unit;
the input synchronous control unit consists of an IDELAY and a carry chain;
the delay synchronous pulse control unit consists of a clock converter, a delay chain and a counting chain;
the narrow pulse control unit, the input synchronous control unit, the delay synchronous control unit and the pulse output control unit are electrically connected in sequence; the narrow pulse control unit, the clock generator and the input synchronous control unit are electrically connected in sequence; the frequency control unit, the Td control unit, and the Tw control unit are electrically connected to the control information input unit, respectively.
4. The phase compensation-based narrow pulse precision time delay synchronization device according to claim 3, further comprising a control information input unit for controlling the frequency control unit, the Td control unit and the Tw control unit.
5. The phase compensation-based narrow-pulse precise time delay synchronization device as claimed in claim 3, wherein the synchronization signal reporting of the narrow-pulse control unit comprises pulse triggering, multiple phase trigger triggered sampling and ADC sampling synchronous reporting modes.
6. The narrow pulse precision time delay synchronizer based on phase compensation is characterized in that the clock generator further comprises a crystal oscillator with high precision, wherein the local clock input by the PLL is more than or equal to one.
7. The narrow pulse precision time delay synchronization device based on phase compensation of claim 6, wherein the clock generator further comprises a PLL input local clock which is a high-precision 200M LVDS differential clock and an output clock which is 500M.
8. The phase compensation-based narrow pulse precise time delay synchronization device as claimed in claim 3, wherein said frequency control unit, Td control unit, Tw control unit and pulse output control unit further comprise but are not limited to single-channel delay pulse information control, which can control multi-channel pulse setting information.
9. The phase compensation-based narrow pulse precise time delay synchronization device according to claim 3, wherein the pulse output control unit further comprises a pulse output for selecting laser pulses, which may be pulses of the same frequency or pulses of a lower frequency.
10. The narrow-pulse precise time delay synchronization device based on phase compensation is characterized in that the time delay synchronization pulse control unit comprises a clock conversion unit, a time delay chain and a pulse width chain; wherein the delay chain comprises IDELAY chain, carry chain, trigger chain and count chain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911128266.3A CN111313870A (en) | 2019-11-18 | 2019-11-18 | Narrow pulse precision time delay synchronization method and device based on phase compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911128266.3A CN111313870A (en) | 2019-11-18 | 2019-11-18 | Narrow pulse precision time delay synchronization method and device based on phase compensation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111313870A true CN111313870A (en) | 2020-06-19 |
Family
ID=71150861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911128266.3A Pending CN111313870A (en) | 2019-11-18 | 2019-11-18 | Narrow pulse precision time delay synchronization method and device based on phase compensation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111313870A (en) |
-
2019
- 2019-11-18 CN CN201911128266.3A patent/CN111313870A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108599743A (en) | A kind of precision digital delay synchronous method based on phase compensation | |
| US8837639B2 (en) | Parallel synchronizing cell with improved mean time between failures | |
| CN105656456B (en) | Circuit and pulse generating method occur for a kind of high-speed, high precision digit pulse | |
| CN109032498B (en) | Waveform quantization synchronization method of multi-FPGA multi-channel acquisition system | |
| US8471607B1 (en) | High-speed frequency divider architecture | |
| CN110649922B (en) | Digital clock frequency multiplier | |
| CN103731136B (en) | Sequential equivalent sampling circuit and method based on delay signals | |
| CN109753481B (en) | Dynamic phase switching system and dynamic phase switching method | |
| CN105067896B (en) | A kind of alien frequencies phase coincidence confusion region characteristic pulse detecting system and detection method | |
| CN111147053B (en) | Glitch-free clock switching circuit | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| CN102790605B (en) | asynchronous signal synchronizer | |
| Büchele et al. | The GANDALF 128-channel time-to-digital converter | |
| CN105242903B (en) | Generating random number apparatus and method | |
| CN108540128B (en) | Clock frequency dividing circuit and frequency dividing method thereof | |
| EP3350928B1 (en) | High-speed programmable clock divider | |
| CN210807207U (en) | Narrow pulse precision time delay synchronization device based on phase compensation | |
| CN111313870A (en) | Narrow pulse precision time delay synchronization method and device based on phase compensation | |
| CN106209090A (en) | A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA | |
| KR101828104B1 (en) | System and method of synchronizing multiple dac apparatus for high speed signal process | |
| CN105245235A (en) | Serial-to-parallel conversion circuit based on clock phase modulation | |
| CN113985960A (en) | Glitch-free switching circuit of system clock and reset implementation method thereof | |
| EP0461291A1 (en) | Clock generation in a multi-chip computersystem | |
| KR102022645B1 (en) | Semiconductor integrated circuit and clock synchronization method | |
| CN115800968A (en) | Low-jitter delay method and system based on clock interpolation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |