CN210807207U - Narrow pulse precision time delay synchronization device based on phase compensation - Google Patents
Narrow pulse precision time delay synchronization device based on phase compensation Download PDFInfo
- Publication number
- CN210807207U CN210807207U CN201921999269.XU CN201921999269U CN210807207U CN 210807207 U CN210807207 U CN 210807207U CN 201921999269 U CN201921999269 U CN 201921999269U CN 210807207 U CN210807207 U CN 210807207U
- Authority
- CN
- China
- Prior art keywords
- control unit
- pulse
- delay
- clock
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Pulse Circuits (AREA)
Abstract
The utility model discloses a narrow pulse precision time delay synchronizer based on phase compensation relates to technical field such as precision finishing, medical treatment, scientific research. The device includes: the pulse generator comprises a clock generator, a narrow pulse control unit, an input synchronization control unit, a delay synchronization pulse control unit, a frequency control unit, a Td (time delay) control unit, a Tw (pulse width) control unit, a control information input unit and a pulse output control unit. The narrow pulse is subjected to synchronous signal control by a narrow pulse control unit, a PLL is additionally utilized to generate a synchronous clock, and then IDELAY and a carry chain are adopted to perform precise synchronous control on the input pulse and the generated clock. The control of pulse delay output and pulse width is realized through the delay synchronous pulse control unit. Through the utility model discloses all designs are all integrated in a slice FPGA, and the circuit is simple reliable, and the integrated level is high, and the consumption is little.
Description
Technical Field
The utility model relates to a technical field such as precision finishing, medical treatment, scientific research especially relates to a laser pulse precision time delay synchro control device.
Background
In ultrafast phenomenon and large-scale precise physical experiments related to the fields of laser precise control, laser nuclear physics, plasma physics, electric discharge and the like, due to the influences of inherent time delay of each subsystem and slight difference of the lengths of signal transmission cables, multi-path trigger signals are delayed and cannot arrive synchronously. An important feature of such experimental research is that the time domain often has strict requirements on the trigger time of each path of signal, which requires a delay synchronization control device to make a pre-delay according to the inherent delay of each path of system before the trigger signal enters each path of system. The delay precision is the most important technical index of the delay synchronization mechanism, which requires precise synchronization control of the action timing sequence of each subsystem.
Generally, the implementation delay method is divided into two main categories, namely special purpose and general purpose. The special delay unit is realized by adopting an analog device, and has the characteristics of high delay precision which can reach 10ps grade, but small dynamic range (less than 50 ns); the general digital delay unit is generally realized by a programmable logic device, and a counter can realize a larger delay dynamic range, but has the defects of limitation of the working frequency of the device and lower precision (generally 5 ns). Meanwhile, the counter starts counting when the external trigger signal arrives, but the phase relation between the external trigger signal and the local clock is random, the maximum jitter value is close to 1 clock cycle, and the phase relation between the counting delay output and the clock is determined, so that the delay output and the external trigger signal have large jitter. Moreover, the input signal has a certain time delay after being processed by the logic circuit, so that the time delay of the external trigger signal and the output signal is larger.
SUMMERY OF THE UTILITY MODEL
In order to overcome the deficiencies of the prior art, the utility model provides a narrow pulse precision time delay synchronizer based on phase compensation. The narrow pulse is subjected to synchronous signal control by a narrow pulse control unit, a PLL is additionally utilized to generate a synchronous clock, and then IDELAY and a carry chain are adopted to perform precise synchronous control on the input pulse and the generated clock. The control of pulse delay output and pulse width is realized through the delay synchronous pulse control unit. Through the utility model discloses all designs are all integrated in a slice FPGA, and the circuit is simple reliable, and the integrated level is high, and the consumption is little.
In order to achieve the above object, the present invention provides a narrow pulse precision time delay synchronizer based on phase compensation.
The utility model discloses a precise time delay synchronizer of narrow pulse based on phase compensation, the condition is as follows, the device includes:
the narrow pulse control unit is used for reporting a synchronous signal to an input narrow pulse;
the clock generator is used for carrying out follow-up output on the narrow pulse clock and frequency multiplication output of the local clock;
an input synchronization control unit for performing a fine clock synchronization control of an input pulse and a generated clock;
the delay synchronous pulse control unit is used for generating clocks with different frequencies, different output delays and different pulse widths;
a pulse output control unit for selecting different pulse outputs;
a frequency control unit for setting a frequency value;
a Td control unit for setting a delay value; and the number of the first and second groups,
a Tw control unit for setting a pulse width value;
the frequency control unit, the Td control unit and the Tw control unit are respectively connected with the delay synchronous pulse control unit;
the input synchronous control unit consists of an IDELAY and a carry chain;
the delay synchronous pulse control unit consists of a clock converter, a delay chain and a counting chain;
the narrow pulse control unit, the synchronous control unit, the delay synchronous control unit and the pulse output control unit are electrically connected in sequence; the narrow pulse control unit, the clock generator and the synchronous control unit are electrically connected in sequence; the frequency control unit, the Td control unit and the Tw control unit are respectively electrically connected to the control information input unit.
Optionally, the apparatus further comprises a control information input unit which controls the frequency control unit, the Td control unit, and the Tw control unit.
Optionally, the reporting of the synchronization signal of the narrow pulse control unit includes a pulse triggering, multiple phase trigger triggering and sampling, and ADC sampling synchronization reporting mode.
Optionally, the clock generator further comprises a crystal oscillator of which the local clock input by the PLL is high precision, and the PLL is equal to or greater than one.
Optionally, the clock generator further comprises a PLL that inputs a local clock that is a high-precision 200M LVDS differential clock and outputs a clock that is 500M.
Optionally, the frequency control unit, the Td control unit, the Tw control unit, and the pulse output control unit further include, but are not limited to, delay pulse information control of a single channel, and may control multi-channel pulse setting information.
Optionally, the pulse output control unit further includes an output pulse for selecting a laser pulse, which may be a pulse with the same frequency or a pulse with a frequency reduced.
Optionally, the delay synchronization pulse control unit further includes a clock conversion unit, a delay chain, and a pulse width chain; the delay chain comprises an IDELAY chain, a carry chain, a trigger chain and a delay chain realized in a counting chain mode.
To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:
the utility model discloses carry out synchro control and follow to the narrow pulse of input, utilize FPGA internal resource, realize controlling output pulse time delay, pulsewidth and frequency, reach the purpose that various scenes were used. All designs are integrated in one FPGA, and the circuit is simple and reliable, high in integration level and low in power consumption.
Drawings
Fig. 1 is a schematic block diagram of the narrow pulse precision time delay synchronization of the present invention;
fig. 2 is a schematic structural diagram of the narrow pulse precision time delay synchronizer of the present invention;
FIG. 3 is a block diagram of the design of the carry chain logic circuit of the present invention;
fig. 4 is a timing diagram of the multi-stage link delay of the present invention.
Detailed Description
All features disclosed in this specification may be combined in any combination, except features and/or steps that are mutually exclusive.
In order to overcome the deficiencies of the prior art, the utility model provides a narrow pulse precision time delay synchronizer based on phase compensation. The narrow pulse is subjected to synchronous signal control by a narrow pulse control unit, a PLL is additionally utilized to generate a synchronous clock, and then IDELAY and a carry chain are adopted to perform precise synchronous control on the input pulse and the generated clock. The control of pulse delay output and pulse width is realized through the delay synchronous pulse control unit. Through the utility model discloses all designs are all integrated in a slice FPGA, and the circuit is simple reliable, and the integrated level is high, and the consumption is little.
The utility model relates to a narrow pulse precision time delay synchronizer based on phase compensation; the device comprises:
the narrow pulse control unit is used for reporting a synchronous signal to the input narrow pulse;
the clock generator is used for carrying out follow-up output and local clock frequency multiplication output on the narrow pulse clock;
an input synchronization control unit for performing a fine clock synchronization control of an input pulse and a generated clock;
the delay synchronous pulse control unit is used for generating clocks with different frequencies, different output delays and different pulse widths;
a pulse output control unit for selecting different pulse outputs;
a frequency control unit for setting a frequency value;
a Td control unit for setting a delay value; and the number of the first and second groups,
a Tw control unit for setting a pulse width value;
the frequency control unit, the Td control unit and the Tw control unit are respectively electrically connected with the delay synchronous pulse control unit;
the input synchronous control unit consists of an IDELAY and a carry chain;
the delay synchronous pulse control unit consists of a clock converter, a delay chain and a counting chain;
the narrow pulse control unit, the input synchronous control unit, the delay synchronous control unit and the pulse output control unit are electrically connected in sequence; the narrow pulse control unit, the clock generator and the input synchronous control unit are electrically connected in sequence; the frequency control unit, the Td control unit, and the Tw control unit are electrically connected to the control information input unit, respectively.
The apparatus further includes a control information input unit which controls the frequency control unit, the Td control unit, and the Tw control unit.
The narrow pulse control unit reports the synchronous signals in a pulse triggering, multi-phase trigger triggering sampling and ADC sampling synchronous reporting mode.
The clock generator also comprises a crystal oscillator with high precision, wherein the local clock input by the PLL is more than or equal to one.
The clock generator also includes a PLL input with a local clock of high precision 200M LVDS differential clock and an output clock of 500M.
The frequency control unit, the Td control unit, the Tw control unit and the pulse output control unit also comprise but are not limited to single-channel delay pulse information control, and can control multi-channel pulse setting information.
The pulse output control unit also comprises an output pulse for selecting laser pulses, which can be pulses with the same frequency or pulses subjected to frequency reduction.
The delay synchronous pulse control unit also comprises a clock conversion unit, a delay chain and a pulse width chain; the delay chain comprises an IDELAY chain, a carry chain, a trigger chain and a delay chain realized in a counting chain mode.
The above and further features and advantages of the present invention will be apparent from the following, more complete description of the invention, taken in conjunction with the accompanying drawings, in which it is to be understood that the described embodiments are merely some, and not all, of the embodiments of the invention.
As shown in fig. 1, a schematic block diagram of a narrow pulse precision time delay synchronization based on phase compensation. The system carries out synchronous signal control on the narrow pulse through a narrow pulse control unit, in addition, a PLL is utilized to generate a synchronous clock, and then IDELAY and a carry chain are adopted to carry out precise synchronous control on the input pulse and the generated clock. The control of pulse delay output and pulse width is realized through the delay synchronous pulse control unit. And finally, the control output of the pulse is realized through the pulse output control unit.
Fig. 2 is a schematic structural diagram of a narrow-pulse precision time delay synchronizer. One specific embodiment of the present apparatus is as follows: the device comprises a pulse control unit PLUSE _ CTRL, a phase-locked loop PLL, a synchronization control unit SYNC _ CTRL, a DELAY pulse synchronization control unit DELAY _ SYNC _ CTRL, a pulse output selection MUX, a DELAY time (Td) \ pulse width (Tw) control unit Td \ Tw CTRL unit and a serial port UART. All modules are realized by using the internal logic resources of the FPGA. The synchronous control of pulse input signals is realized by utilizing a PLL and a logic circuit, the input differential signals are LVDS interfaces, and the clock frequency is 200M. Secondly, the precise compensation of the link delay is realized by utilizing the internal input delay unit (IDELAY) [1: N ] and CARRY chain (CARRY4) [1: N ] resources, wherein N is more than or equal to 1, which is determined according to the specific implementation situation. In addition, the clock conversion unit (CLKSWITCH) [1: N ] is used for realizing different output pulse conversion, wherein N is larger than or equal to 1 and is determined according to the number of interfaces required to be output; the DELAY chain (DELAY CHAIN) [1: N ] is used for realizing precise DELAY (DELAY) control, wherein N is more than or equal to 1 and is determined according to specific implementation conditions; the pulse width control CHAIN (PW CHAIN) [1: N ] is used to realize precise pulse width control, wherein N is more than or equal to 1, and is determined according to specific implementation conditions. And finally, realizing the selection control of pulse output through MUX resources.
FIG. 3 is a block diagram of the carry chain logic circuit design. A plurality of CARRY chain (CARRY4) units are used for link connection, and precise delay control is realized by using the CARRY chain. Wherein N is more than or equal to 1, which is determined according to specific implementation conditions.
As shown in fig. 4, it is a timing diagram of the delay of the clock through different numbers of links. The larger the link passes through, the larger the time delay is, and the multiple of the time delay and the number of the links are in direct proportion.
The above-mentioned embodiments further describe the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention. It should be understood that any modification, equivalent replacement, or improvement made by those skilled in the art without departing from the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A narrow pulse precision time delay synchronizer based on phase compensation is characterized by comprising:
the narrow pulse control unit is used for reporting a synchronous signal to an input narrow pulse;
the clock generator is used for carrying out follow-up output on the narrow pulse clock and frequency multiplication output of the local clock;
an input synchronization control unit for performing a fine clock synchronization control of an input pulse and a generated clock;
the delay synchronous pulse control unit is used for generating clocks with different frequencies, different output delays and different pulse widths;
a pulse output control unit for selecting different pulse outputs;
a frequency control unit for setting a frequency value;
a Td control unit for setting a delay value; and the number of the first and second groups,
a Tw control unit for setting a pulse width value;
the frequency control unit, the Td control unit and the Tw control unit are respectively connected with the delay synchronous pulse control unit;
the input synchronous control unit consists of an IDELAY and a carry chain;
the delay synchronous pulse control unit consists of a clock converter, a delay chain and a counting chain;
the narrow pulse control unit, the synchronous control unit, the delay synchronous control unit and the pulse output control unit are electrically connected in sequence; the narrow pulse control unit, the clock generator and the synchronous control unit are electrically connected in sequence; the frequency control unit, the Td control unit, and the Tw control unit are electrically connected to the control information input unit, respectively.
2. The narrow pulse precision time delay synchronization device based on phase compensation according to claim 1,
the system is characterized by further comprising a control information input unit, wherein the control information input unit controls the frequency control unit, the Td control unit and the Tw control unit.
3. The phase compensation-based narrow-pulse precise time delay synchronization device as claimed in claim 1, wherein the synchronization signal reporting of the narrow-pulse control unit comprises pulse triggering, multiple phase trigger triggering sampling and ADC sampling synchronous reporting modes.
4. The narrow pulse precision time delay synchronizer based on phase compensation is characterized in that the clock generator further comprises a crystal oscillator with high precision, wherein the local clock input by the PLL is more than or equal to one.
5. The narrow pulse precision time delay synchronizer based on phase compensation of claim 4, wherein the clock generator further comprises a PLL input local clock which is a high precision 200M LVDS differential clock and an output clock which is 500M.
6. The phase compensation-based narrow pulse precision time delay synchronization device of claim 1, wherein the frequency control unit, the Td control unit, the Tw control unit and the pulse output control unit further comprise but are not limited to single-channel delay pulse information control, and can control multi-channel pulse setting information.
7. The phase compensation-based narrow pulse precise time delay synchronization device according to claim 1, wherein the pulse output control unit further comprises an output pulse for selecting laser pulses, which may be common-frequency pulses or frequency-down pulses.
8. The narrow-pulse precise time delay synchronization device based on phase compensation is characterized in that the time delay synchronization pulse control unit comprises a clock conversion unit, a time delay chain and a pulse width chain; wherein the delay chain comprises IDELAY chain, carry chain, trigger chain and count chain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921999269.XU CN210807207U (en) | 2019-11-18 | 2019-11-18 | Narrow pulse precision time delay synchronization device based on phase compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921999269.XU CN210807207U (en) | 2019-11-18 | 2019-11-18 | Narrow pulse precision time delay synchronization device based on phase compensation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210807207U true CN210807207U (en) | 2020-06-19 |
Family
ID=71232469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921999269.XU Active CN210807207U (en) | 2019-11-18 | 2019-11-18 | Narrow pulse precision time delay synchronization device based on phase compensation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210807207U (en) |
-
2019
- 2019-11-18 CN CN201921999269.XU patent/CN210807207U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108599743A (en) | A kind of precision digital delay synchronous method based on phase compensation | |
| US10020655B2 (en) | Global synchronous pulse width modulation system and method for distributed grid-connected inverter system | |
| US9054681B2 (en) | High speed duty cycle correction and double to single ended conversion circuit for PLL | |
| US8837639B2 (en) | Parallel synchronizing cell with improved mean time between failures | |
| CN105656456B (en) | Circuit and pulse generating method occur for a kind of high-speed, high precision digit pulse | |
| US8471607B1 (en) | High-speed frequency divider architecture | |
| CN103731136B (en) | Sequential equivalent sampling circuit and method based on delay signals | |
| CN110649922B (en) | Digital clock frequency multiplier | |
| CN102707766B (en) | signal synchronization device | |
| CN103427798A (en) | Multiphase clock generation circuit | |
| CN105067896B (en) | A kind of alien frequencies phase coincidence confusion region characteristic pulse detecting system and detection method | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| CN110311672B (en) | Low-delay high-frequency clock frequency division circuit, frequency divider and frequency division method | |
| CN104467750B (en) | For the implementation method of technique of laser range gated imaging pulsewidth precision impulse generator high | |
| US11539355B2 (en) | Systems and methods for generating a controllable-width pulse signal | |
| CN102790605B (en) | asynchronous signal synchronizer | |
| CN210807207U (en) | Narrow pulse precision time delay synchronization device based on phase compensation | |
| KR100273238B1 (en) | Time delay compensation circuit in clock buffer | |
| CN108540128B (en) | Clock frequency dividing circuit and frequency dividing method thereof | |
| CN204836104U (en) | Anti -jamming circuit based on logic time delay locking | |
| CN111313870A (en) | Narrow pulse precision time delay synchronization method and device based on phase compensation | |
| US9455710B2 (en) | Clock enabling circuit | |
| CN106209090A (en) | A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA | |
| CN207884576U (en) | A kind of digital frequency multiplier | |
| CN105245235A (en) | Serial-to-parallel conversion circuit based on clock phase modulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |