CN115800968A - Low-jitter delay method and system based on clock interpolation method - Google Patents

Abstract

The invention discloses a low-jitter delay method and a low-jitter delay system based on a clock interpolation method, which comprise the following steps of: adjusting the clock time sequence of the digital circuit to obtain a plurality of paths of clock signals with phase difference for driving the microprocessor; the clock signal is used for driving the microprocessor to perform trigger time delay on an external pulse signal to obtain a time delay output signal; selecting the delay output signal by using a logic gate to obtain a low-jitter delay signal; and utilizing a delay line chip to carry out micro adjustment on the delay time output by the delay signal, and outputting the adjusted low-jitter delay signal. Compared with the prior art, the low-jitter delay circuit scheme is a digital circuit method, the circuit structure scheme is simpler, the size is smaller, the implementation mode cost is lower, and the clock frequency of the whole system can be indirectly improved through the method, so that the jitter of the delay signal is reduced.

Description

Low-jitter delay method and system based on clock interpolation method

Technical Field

The invention belongs to the technical field of high-precision low-jitter large dynamic delay, and particularly relates to a low-jitter delay method and system based on a clock interpolation method.

Background

In an electronic system, a delay system has important applications in the processes of signal caching, beam forming and data processing, particularly in the process of acquiring signals by radar echo signals, the delay system is an indispensable ring, the maximum delay time of the delay system corresponds to the maximum detection distance of the radar signals, the minimum delay time of the delay system corresponds to the minimum distance precision which can be distinguished by the system, and because carriers of a plurality of radar signals are electromagnetic waves, the transmission speed of the delay system is extremely high, and in order to reduce the problem of reduction of the distance measurement precision caused by the jitter of delay circuit signals, the jitter range of the delay system is required to be as small as possible.

At present, most of delay systems are designed by adopting a method of a single chip microcomputer and a delay line chip or an FPGA and a delay line chip to realize the design of a large-dynamic high-precision delay system, the single chip microcomputer or the FPGA is used for realizing the large-range adjustment of delay time, and the delay time is finely adjusted by utilizing the delay line. However, in an actual application scenario, because the external trigger signal is not synchronized with the internal clock of the single chip or FPGA, most of the complex digital circuits are synchronous sequential logic circuits, and the state of the circuit can be changed only when the next clock pulse arrives, so that in the process of responding to the external pulse signal, the time required from the establishment of the external pulse signal to the response of the digital circuit changes every time, which causes the jitter of the output delay signal, and the jitter time is 1 clock cycle of the digital circuit, and when the system has a high requirement on the jitter of the signal, the phenomenon is not negligible.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a low-jitter delay system design method based on a clock interpolation method, so as to solve the problem of high jitter of the existing delay system.

In order to achieve the purpose, the invention provides the following scheme:

a low-jitter delay method based on a clock interpolation method comprises the following steps:

adjusting the clock time sequence of the digital circuit to obtain a plurality of paths of clock signals with phase difference for driving the microprocessor;

the clock signal is used for driving the microprocessor to trigger and delay an external pulse signal to obtain a delay signal;

selecting the delay signal by using a logic gate to obtain a low-jitter delay signal;

and utilizing a delay line chip to carry out micro adjustment on the delay time output by the delay signal, and outputting the adjusted low-jitter delay signal.

Optionally, the phase difference is 2 pi/n, where n represents n digital circuits.

Optionally, the logic gate selects the delayed output signal by using a logic or gate.

Optionally, the method for selecting the low jitter delay signal by using a logic or gate includes:

and selecting and outputting the output signal responded by the digital circuit fastest.

Optionally, the adjusted jitter time estimation method for the low-jitter delay signal includes:

wherein t represents the time when the rising edge of the external signal appears; n represents n-way digital circuitry; t represents the clock period of the internal clock of the digital circuit; h (t) represents the fastest response time required from the establishment of the external trigger signal to the beginning of the response of the digital circuit; WT indicates the jitter degree of the delay signal.

The invention also provides a low-jitter delay system based on the clock interpolation method, which comprises the following steps: the device comprises an external clock module, a delay triggering module, a logic processing module and a delay adjusting module;

the external clock module is used for adjusting the clock time sequence of the digital circuit to obtain a clock signal which is used for driving the microprocessor and has a phase difference;

the delay triggering module is used for driving the microprocessor to trigger an external pulse signal based on the clock signal and the delay period and making delay response on the external signal to obtain a delay signal;

the logic processing module is used for carrying out selective processing on the delay signal to obtain a low-jitter delay signal;

the delay adjusting module is used for carrying out fine adjustment on the low-jitter delay signal to obtain the adjusted low-jitter delay signal.

Optionally, the phase difference of the internal clock signals of the microcontroller is 2 pi/n, where n denotes an n-way digital circuit.

Optionally, the logic processing module selects the delay signal by using a logic or gate.

Optionally, the method for selecting the delay signal by the logic or gate includes:

and selecting and outputting the output signal responded by the digital circuit fastest.

Optionally, the adjusted jitter time evaluation method for the low jitter delay signal includes:

wherein t represents the time when the rising edge of the external signal appears; n represents n-way digital circuitry; t represents the clock period of the internal clock of the digital circuit; h (t) represents the fastest response time required from the establishment of the external trigger signal to the beginning of the response of the digital circuit; WT indicates the jitter degree of the delay signal.

The invention has the beneficial effects that:

the invention discloses a low-jitter delay method and a low-jitter delay system based on a clock interpolation method, which realize accurate controllable delay of external trigger pulses by adjusting and matching internal clocks of a multi-channel single chip microcomputer or an FPGA (field programmable gate array) and combining a precise delay chip, and can reduce the jitter of output signals to 1/n (wherein n represents that n digital circuits trigger external signals simultaneously) under the condition of not directly improving the clock frequency of the single chip microcomputer by aiming at the condition that the output signals of a digital circuit can generate 1 clock period jitter when the digital circuit triggers the external pulses. Compared with the prior art, the low-jitter delay circuit scheme is a digital circuit method, the circuit structure scheme is simpler, the size is smaller, the implementation mode cost is lower, and the clock frequency of the whole system can be indirectly improved through the method, so that the jitter of the delay signal is reduced.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a timing diagram of a delay triggered external signal using a single-channel digital circuit;

FIG. 2 is a schematic flow chart of a low jitter delay method based on clock interpolation according to an embodiment of the present invention;

FIG. 3 is a block diagram of a circuit implementation of a single chip according to an embodiment of the invention;

FIG. 4 is a timing diagram illustrating the delay triggering of an external signal by a digital circuit with n fixed phase difference clocks according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a low jitter delay system based on a clock interpolation method according to a second embodiment of the present invention;

fig. 6 is a structure diagram of an FPGA circuit according to a third embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

It can be seen from fig. 1 that when the external signal is not synchronized with the internal clock frequency of the digital circuit, the rising edge of the external signal appears at any time of the clock signal of the digital circuit, i.e. the time T ∈ [0, T ] when the rising edge of the external signal is far from the next clock signal of the single chip, where T represents the clock period of the internal clock of the digital circuit. Most of complex digital circuits are synchronous sequential logic circuits, and the state of the circuit can be changed only when the next clock pulse arrives, so that the delay signal output by the digital circuit has jitter of one clock period, which brings great influence on the signal output by the delay system.

Example one

As shown in fig. 2, a schematic flow chart of a low jitter delay method based on a clock interpolation method according to the present application is shown; the method comprises the following steps:

s1, adjusting a clock time sequence of a digital circuit to obtain a plurality of paths of clock signals with phase difference for driving a microprocessor;

as shown in fig. 3, which is a circuit implementation structure diagram of this embodiment, in this embodiment, a total of eight Microprocessors (MCUs) are used for external triggering, the microprocessors use STM32F103 series single-chip microcomputers, and the clock frequency of the single-chip microcomputers is 72MHZ, that is, 1 clock cycle is 13.89ns.

The phase difference of the internal clock signals of each MCU is controlled by an external clock module circuit, so that the phase difference of the clock signals in each MCU is pi/4, namely the phase difference of the clock signals of the adjacent MCUs is 1.6ns.

S2, driving a microprocessor to trigger and delay an external pulse signal by using a clock signal to obtain a delay signal;

the 8 MCU with certain phase difference is used for triggering the same external signal, and the timer in the MCU is controlled by the communication control module to make corresponding time delay and output

S3, selecting the delay signal by using a logic gate to obtain a low-jitter delay signal;

connecting the trigger delay signal output by the MCU to a logic OR gate, and performing selective processing on the output delay signal by using the logic OR gate to obtain a low-jitter delay signal;

as shown in fig. 4, when there are n digital circuits to trigger the same external signal, the clock phase difference between two adjacent digital circuits is 2 pi/n (i.e. the clock interval Δ T = T/n), and it can be found from the timing diagram of fig. 4 that, for a single-circuit signal, the time T that needs to wait for the external signal to be triggered by the digital circuit is in the range of [0,t []. However, in an n-way digital circuit, when the first external pulse occurs, it can be found from the clock timing of the n-way digital circuit that at t ₁₁ ，t ₂₁ ，…，t _n1 ]Middle t ₁₁ At a minimum, the first pulse is responded to and output most quickly by the digital circuit of clock1, so that the first output pulse is synchronized with clock 1; at the occurrence of the second pulse, at [ t ] ₁₁ ，t ₂₂ ，…，t _n2 ]Middle t ₂₂ At minimum, the second pulse is responded to and output by the digital circuit of clock2 most quickly, and the second output pulse is synchronous with clock 2; and finally, controlling the signal response delay output of the n-path digital circuit through a logic OR gate, and selectively outputting one path of signal which is responded by the digital circuit fastest every time to obtain a low-jitter delay signal.

And S4, carrying out micro adjustment on the delay time output by the delay signal by using the delay line chip, and outputting the adjusted low-jitter delay signal.

And the delay signal with low jitter passes through a delay chip, and the delay line has higher-precision delay adjustment capability to realize precise adjustment of delay time, so that the final delay signal with low jitter is obtained.

When the same external signal is triggered by n digital circuits with certain phase difference of clocks (the phase difference of clocks of two adjacent digital circuits is

) The jitter time of the finally output delay signal becomes 1/n of the original jitter time as can be obtained from the following mathematical model.

Wherein t represents the time when the rising edge of the external signal appears; n represents n-way digital circuitry; t represents the clock period of the internal clock of the digital circuit; h (t) represents the fastest response time required from the establishment of the external trigger signal to the beginning of the response of the digital circuit; WT indicates the jitter degree of the delay signal.

Example two

As shown in fig. 5, the present invention further provides a low jitter delay system based on clock interpolation, including: the device comprises an external clock module, a delay triggering module, a logic processing module and a delay adjusting module;

the external clock module is used for adjusting the clock time sequence of the digital circuit to obtain a clock signal which is used for driving the microprocessor and has a phase difference;

the specific working process comprises the following steps:

the external clock module circuit controls the phase difference of the internal clock signals of each MCU, so that the phase difference of the clock signals inside each MCU is 2 pi/n, and n represents n paths of digital circuits.

The delay triggering module is used for driving the microprocessor to trigger an external pulse signal based on the clock signal and the delay period and making delay response to the external signal to obtain a delay signal;

the logic processing module is used for carrying out selective processing on the delay signal to obtain a low-jitter delay signal;

the working process of the logic processing module comprises the following steps:

connecting the trigger delay signal output by the MCU to a logic OR gate, and performing selective processing on the output delay signal by using the logic OR gate to obtain a low-jitter delay signal;

as shown in fig. 4, when there are n digital circuits to trigger the same external signal, the clock phase difference between two adjacent digital circuits is 2 pi/n (i.e. the clock interval Δ T = T/n), and it can be found from the timing diagram of fig. 4 that, for a single-circuit signal, the time T that needs to wait for the external signal to be triggered by the digital circuit is in the range of [0,t []. However, in an n-way digital circuit, when the first external pulse occurs, it can be found from the clock timing of the n-way digital circuit at t ₁₁ ，t ₂₁ ，…，t _n1 ]Middle t ₁₁ At a minimum, the first pulse is responded to and output most quickly by the digital circuit of clock1, so that the first output pulse is synchronized with clock 1; at the occurrence of the second pulse, at [ t ] ₁₁ ，t ₂₂ ，…，t _n2 ]Middle t ₂₂ At minimum, the second pulse is responded to and output by the digital circuit of clock2 most quickly, and the second output pulse is synchronous with clock 2; and finally, controlling the signal response delay output of the n-path digital circuit through a logic OR gate, and selectively outputting one path of signal which is responded by the digital circuit fastest every time to obtain a low-jitter delay signal.

The delay adjusting module is used for carrying out fine adjustment on the low-jitter delay signal to obtain the adjusted low-jitter delay signal.

And the delay signal with low jitter passes through a delay chip, and the delay line has higher-precision delay adjustment capability to realize precise adjustment of delay time, so that the final delay signal with low jitter is obtained.

When the same external signal is triggered by n digital circuits with certain phase difference of clocks (the phase difference of clocks of two adjacent digital circuits is

) The jitter time of the finally output delay signal becomes 1/n of the original jitter time as can be obtained from the following mathematical model.

Wherein t represents the time when the rising edge of the external signal appears; n represents n-way digital circuitry; t represents the clock period of the internal clock of the digital circuit; h (t) represents the fastest response time required from the establishment of the external trigger signal to the beginning of the response of the digital circuit; WT indicates the degree of jitter of the delayed signal.

The low-jitter delay system based on the clock interpolation method also comprises a communication control module, and the communication control module is used for adjusting the delay time of the system in real time from the outside.

EXAMPLE III

In the embodiment, an FPGA or a CPLD is used as the MCU, a packaged clock network is present in the FPGA, and the clock frequency and the phase difference of the I/O port of the FPGA can be set by setting the IP core of the clock guide in the programming stage.

As can be seen from fig. 6, in the present embodiment, four paths of I/O ports are used to perform delay triggering on an external input signal, and a clock phase difference between two adjacent paths of I/O ports is pi/2. Setting the clock frequency to 300MHZ, the clock period is 3.33ns, so the time interval of the adjacent clock signals of the FPGAI/O port is different by 0.83ns. In the embodiment, the communication control module selects an RS 232-TTL communication circuit, outputs the delay signal to a logic control OR gate circuit, performs logic processing on the delay output signal with high jitter through a logic circuit to obtain delay signal output with low jitter, and finally performs precise adjustment on delay time through a delay line chip to obtain the delay signal meeting the requirement.

The above-described embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solutions of the present invention can be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are within the scope of the present invention defined by the claims.

Claims (10)

1. A low-jitter delay method based on a clock interpolation method is characterized by comprising the following steps:

adjusting the clock time sequence of the digital circuit to obtain a plurality of paths of clock signals with phase difference for driving the microprocessor;

the clock signal is used for driving the microprocessor to trigger and delay an external pulse signal to obtain a delay signal;

selecting the delay signal by using a logic gate to obtain a low-jitter delay signal;

and utilizing a delay line chip to carry out micro adjustment on the delay time output by the delay signal, and outputting the adjusted low-jitter delay signal.

2. The clock interpolation method-based low-jitter delay method according to claim 1, wherein the phase difference is 2 pi/n, where n represents n digital circuits.

3. The clock interpolation-based low-jitter delay method of claim 1, wherein the logic gate selects the delayed output signal using a logic or gate.

4. The clock interpolation-based low-jitter delay method of claim 3, wherein the selecting the low-jitter delay signal using a logical OR gate comprises:

and selecting and outputting the output signal responded by the digital circuit fastest.

5. The clock interpolation-based low-jitter delay method according to claim 1, wherein the adjusted jitter time estimation method for the low-jitter delay signal comprises:

wherein, t represents the time when the rising edge of the external signal appears; n represents n-way digital circuits; t represents the clock period of the internal clock of the digital circuit; h (t) represents the fastest response time required from the establishment of the external trigger signal to the time when the digital circuit starts responding; WT indicates the jitter degree of the delay signal.

6. A low-jitter delay system based on clock interpolation, comprising: the device comprises an external clock module, a delay triggering module, a logic processing module and a delay adjusting module;

the external clock module is used for adjusting the clock time sequence of the digital circuit to obtain a clock signal which is used for driving the microprocessor and has a phase difference;

the delay triggering module is used for driving the microprocessor to trigger an external pulse signal based on the clock signal and the delay period and making delay response on the external signal to obtain a delay signal;

the logic processing module is used for carrying out selective processing on the delay signal to obtain a low-jitter delay signal;

the delay adjusting module is used for carrying out fine adjustment on the low-jitter delay signal to obtain the adjusted low-jitter delay signal.

7. The clock interpolation based low-jitter delay system of claim 6, wherein the phase difference of the internal clock signal of the microcontroller is 2 pi/n, where n represents n digital circuits.

8. The clock interpolation-based low-jitter delay system of claim 6, wherein the logic processing module selects the delay signal by using a logic OR gate.

9. The clock interpolation based low-jitter delay system of claim 8, wherein the logic or gate selects the delay signal by:

and selecting and outputting the output signal responded by the digital circuit fastest.

10. The clock interpolation-based low-jitter delay system of claim 6, wherein the adjusted jitter time estimation method of the low-jitter delay signal comprises:

wherein t represents the time when the rising edge of the external signal appears; n represents n-way digital circuitry; t represents the clock period of the internal clock of the digital circuit; h (t) represents the fastest response time required from the establishment of the external trigger signal to the beginning of the response of the digital circuit; WT indicates the degree of jitter of the delayed signal.

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