CN111193509B - Automatic calibration method and system for source synchronous data sampling points - Google Patents
Automatic calibration method and system for source synchronous data sampling points Download PDFInfo
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- CN111193509B CN111193509B CN201911416315.3A CN201911416315A CN111193509B CN 111193509 B CN111193509 B CN 111193509B CN 201911416315 A CN201911416315 A CN 201911416315A CN 111193509 B CN111193509 B CN 111193509B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Abstract
The invention provides an automatic calibration method and system for source synchronous data sampling points, comprising the following steps: step M1: according to the control information of the alternating data transmission, the alternating data is transmitted at the data source to obtain the result information of the alternating data transmission; step M2: according to the high-low alternating data transmission result information, the DFFs unit performs positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information; step M3: comparing the positive edge sampling result information and the negative edge sampling result information at the positive edge of the next clock according to the positive edge sampling result information and the negative edge sampling result information to obtain judgment result information; step M4: and acquiring automatic calibration result information of the sampling points of the source synchronous data according to the judgment result information. The invention can ensure accurate and stable data sampling of the high-speed source synchronous system when signal delay is unstable due to temperature, humidity, electromagnetic interference and the like.
Description
Technical Field
The invention relates to the field of calibration circuits, in particular to an automatic calibration method and an automatic calibration system for source synchronous data sampling points.
Background
In a source synchronous clock system, data and a source synchronous clock signal are synchronously transmitted, and the flight time of the two signals is guaranteed to be completely consistent, so that the complete correct sequence can be obtained at a receiving end as long as the time sequence at the transmitting end is correct. The stability of the whole system in time sequence is completely embodied in the matching degree of data and clocks, including the matching of transmission delay, the matching of device performance and the like, so long as the conditions of the data and the clock are completely the same, the time sequence of the system can be ensured to be absolutely correct, and the highest clock frequency of the system is not limited. Of course, for any data reception, certain setup and hold times must be met, as well as the source synchronous clock system, mainly in terms of timing requirements between the data signal and the clock signal. The clock sampling edges are optimally aligned to the central portion of the data signal, as shown, so that the most adequate setup and hold times are ensured. For high speed source synchronous systems, if the delay of the clock and data arrival at the sampling end or the eye pattern changes slightly (due to temperature, humidity, electromagnetic interference, etc.), this can result in setup or hold times that are not satisfactory. The automatic calibration circuit for the sampling point is designed, and can ensure accurate and stable sampling by automatic calibration regardless of the phase relation between a clock and data at a sampling end.
Patent document CN110462532a discloses an automatic calibration method for measuring circuits, for example in industrial automation or processing processes, where only one person is required to manage the whole procedure. The assembly is a calibrator (11) held by the field staff and connectable to the start of the measurement circuit to give pulses. The amount to be measured/calibrated is not limited. The measurement results can be seen at the end of the measuring circuit on the screen of the control room, i.e. the DCS (13). According to an alternative embodiment, the measured values may be directed to a dedicated server (14) via an OPC connection and returned to the calibrator (11) wirelessly or via ethernet. An alternative is to use a smart device (16) that the staff has, containing a suitable application, to which measurement data can be sent over the network, and in which the data can also be presented in a user-friendly way. Thus, data can be sent onward to the calibrator (11) on site via the BT connection. A third alternative is to send the measurement results directly from the control room (13) to the calibrator (11), whereby the data can be sent using a 3G/4G/5G network, wifi, bluetooth or ethernet connection. The delay module (15) manages the mutual time synchronization of data, i.e. pairs of numbers. The data may be stored in a spreadsheet, matrix or graphical form at a desired place, such as in the calibrator (11) own memory or in a desired server in the cloud, for example. The patent still leaves room for improvement in accuracy and stability of calibration.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide an automatic calibration method and an automatic calibration system for a source synchronous data sampling point.
The invention provides a method for automatically calibrating a source synchronous data sampling point, which comprises the following steps: step M1: according to the control information of the alternating data transmission, the alternating data is transmitted at the data source to obtain the result information of the alternating data transmission; step M2: according to the high-low alternating data transmission result information, the DFFs unit performs positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information; step M3: comparing the positive edge sampling result information and the negative edge sampling result information at the positive edge of the next clock according to the positive edge sampling result information and the negative edge sampling result information to obtain judgment result information; step M4: and acquiring automatic calibration result information of the sampling points of the source synchronous data according to the judgment result information.
Preferably, the step M2 includes: step M2.1: and according to the high-low alternating data transmission result information, the two groups of DFFs perform positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information.
Preferably, the step M4 includes: step M4.1: acquiring the same judgment result information or different judgment result information according to the judgment result information; step M4.2: and according to the same judging result information, notifying the PLL control circuit to send a positive phase shift control signal.
Preferably, the step M4 further includes: step M4.3: and according to the different judging result information, notifying the PLL control circuit to send a negative phase shift control signal.
Preferably, the method further comprises: step M5: and (3) repeating the steps M1 to M4, and performing automatic calibration on the source synchronous data sampling points for a plurality of times.
The invention provides an automatic calibration system for a source synchronous data sampling point, which comprises the following components: module M1: according to the control information of the alternating data transmission, the alternating data is transmitted at the data source to obtain the result information of the alternating data transmission; module M2: according to the high-low alternating data transmission result information, the DFFs unit performs positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information; module M3: comparing the positive edge sampling result information and the negative edge sampling result information at the positive edge of the next clock according to the positive edge sampling result information and the negative edge sampling result information to obtain judgment result information; module M4: and acquiring automatic calibration result information of the sampling points of the source synchronous data according to the judgment result information.
Preferably, the module M2 comprises: module M2.1: and according to the high-low alternating data transmission result information, the two groups of DFFs perform positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information.
Preferably, the module M4 comprises: module M4.1: acquiring the same judgment result information or different judgment result information according to the judgment result information; module M4.2: and according to the same judging result information, notifying the PLL control circuit to send a positive phase shift control signal.
Preferably, the module M4 further comprises: module M4.3: and according to the different judging result information, notifying the PLL control circuit to send a negative phase shift control signal.
Preferably, the method further comprises: module M5: repeating the modules M1 to M4, and carrying out automatic calibration on the source synchronous data sampling points for a plurality of times.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention can adapt to all source synchronous systems with different delays by using a set of circuit schemes;
2, the invention can ensure accurate and stable data sampling of the high-speed source synchronous system when signal delay caused by temperature, humidity, electromagnetic interference and the like is unstable.
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Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
fig. 1 is a schematic diagram of a circuit frame according to an embodiment of the invention.
Fig. 2 is a schematic diagram of the case where the start state of the system operation mechanism is the same as the positive and negative edge data in the embodiment of the present invention.
FIG. 3 is a schematic diagram of a system operating mechanism with opposite positive and negative edge data in the initial state according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.
As shown in fig. 1-3, the method for automatically calibrating the sampling point of the source synchronous data according to the present invention includes: step M1: according to the control information of the alternating data transmission, the alternating data is transmitted at the data source to obtain the result information of the alternating data transmission; step M2: according to the high-low alternating data transmission result information, the DFFs unit performs positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information; step M3: comparing the positive edge sampling result information and the negative edge sampling result information at the positive edge of the next clock according to the positive edge sampling result information and the negative edge sampling result information to obtain judgment result information; step M4: and acquiring automatic calibration result information of the sampling points of the source synchronous data according to the judgment result information.
Preferably, the step M2 includes: step M2.1: and according to the high-low alternating data transmission result information, the two groups of DFFs perform positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information.
Preferably, the step M4 includes: step M4.1: acquiring the same judgment result information or different judgment result information according to the judgment result information; step M4.2: and according to the same judging result information, notifying the PLL control circuit to send a positive phase shift control signal.
Preferably, the step M4 further includes: step M4.3: and according to the different judging result information, notifying the PLL control circuit to send a negative phase shift control signal.
Preferably, the method further comprises: step M5: and (3) repeating the steps M1 to M4, and performing automatic calibration on the source synchronous data sampling points for a plurality of times.
Specifically, in one embodiment, as shown in fig. 2 and fig. 3, in a method for automatically calibrating a sampling point of source synchronous data, high-low alternating data is required to be sent at a data source, two sets of DFFs respectively perform positive edge sampling and negative edge sampling, and the two sets of data are compared at the positive edge of the next clock. If the two signals are the same, the PLL control circuit is informed to send a positive phase shift control signal; if the opposite is true, the PLL control circuit is notified to send a negative phase shift control signal. Over time (the timer counts to a given value), the clock rising edge will be aligned with the central portion of the data.
The invention provides an automatic calibration system for a source synchronous data sampling point, which comprises the following components: module M1: according to the control information of the alternating data transmission, the alternating data is transmitted at the data source to obtain the result information of the alternating data transmission; module M2: according to the high-low alternating data transmission result information, the DFFs unit performs positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information; module M3: comparing the positive edge sampling result information and the negative edge sampling result information at the positive edge of the next clock according to the positive edge sampling result information and the negative edge sampling result information to obtain judgment result information; module M4: and acquiring automatic calibration result information of the sampling points of the source synchronous data according to the judgment result information.
Preferably, the module M2 comprises: module M2.1: and according to the high-low alternating data transmission result information, the two groups of DFFs perform positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information.
Preferably, the module M4 comprises: module M4.1: acquiring the same judgment result information or different judgment result information according to the judgment result information; module M4.2: and according to the same judging result information, notifying the PLL control circuit to send a positive phase shift control signal.
Preferably, the module M4 further comprises: module M4.3: and according to the different judging result information, notifying the PLL control circuit to send a negative phase shift control signal.
Preferably, the method further comprises: module M5: repeating the modules M1 to M4, and carrying out automatic calibration on the source synchronous data sampling points for a plurality of times.
Specifically, in one embodiment, a source synchronous data sampling point auto-calibration system includes: a phase-shifter PLL unit, a DFFs unit, a data comparison circuit unit, a PLL control circuit unit and a timer unit; wherein, the liquid crystal display device comprises a liquid crystal display device,
the phase-shifting PLL unit is a phase-locked loop capable of shifting the clock phase, wherein the clock phase shifts to the right when an effective signal is input to the +end, and the clock phase shifts to the left when an effective signal is input to the end;
the DFFs unit is used for sampling data;
a data comparison circuit unit: for comparison of positive and negative edge sample data;
PLL control circuit unit: generating a phase shift control signal according to the data comparison result;
a timer unit: for timing, and after a given time, generates a control signal to turn off the PLL control circuit.
The invention can adapt to all source synchronous systems with different delays by using a set of circuit schemes; the invention can ensure accurate and stable data sampling of the high-speed source synchronous system when signal delay is unstable due to temperature, humidity, electromagnetic interference and the like.
Those skilled in the art will appreciate that the invention provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.
Claims (6)
1. An automatic calibration method for sampling points of source synchronous data, which is characterized by comprising the following steps:
step M1: according to the control information of the alternating data transmission, the alternating data is transmitted at the data source to obtain the result information of the alternating data transmission;
step M2: according to the high-low alternating data transmission result information, the DFFs unit performs positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information;
step M3: comparing the positive edge sampling result information and the negative edge sampling result information at the positive edge of the next clock according to the positive edge sampling result information and the negative edge sampling result information to obtain judgment result information;
step M4: acquiring automatic calibration result information of a source synchronous data sampling point according to the judgment result information;
the step M4 includes:
step M4.1: acquiring the same judgment result information or different judgment result information according to the judgment result information;
step M4.2: according to the same judging result information, notifying the PLL control circuit to send a positive phase shift control signal;
step M4.3: and according to the different judging result information, notifying the PLL control circuit to send a negative phase shift control signal.
2. The method for automatically calibrating source synchronous data sampling points according to claim 1, wherein the step M2 comprises:
step M2.1: and according to the high-low alternating data transmission result information, the two groups of DFFs perform positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information.
3. The method for automatically calibrating a source synchronous data sampling point according to claim 1, further comprising: step M5: and (3) repeating the steps M1 to M4, and performing automatic calibration on the source synchronous data sampling points for a plurality of times.
4. A system for automatic calibration of source synchronous data sampling points, comprising:
module M1: according to the control information of the alternating data transmission, the alternating data is transmitted at the data source to obtain the result information of the alternating data transmission;
module M2: according to the high-low alternating data transmission result information, the DFFs unit performs positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information;
module M3: comparing the positive edge sampling result information and the negative edge sampling result information at the positive edge of the next clock according to the positive edge sampling result information and the negative edge sampling result information to obtain judgment result information;
module M4: acquiring automatic calibration result information of a source synchronous data sampling point according to the judgment result information;
the module M4 includes:
module M4.1: acquiring the same judgment result information or different judgment result information according to the judgment result information;
module M4.2: according to the same judging result information, notifying the PLL control circuit to send a positive phase shift control signal;
module M4.3: and according to the different judging result information, notifying the PLL control circuit to send a negative phase shift control signal.
5. The system of claim 4, wherein the module M2 comprises:
module M2.1: and according to the high-low alternating data transmission result information, the two groups of DFFs perform positive edge sampling and negative edge sampling to obtain positive edge sampling result information and negative edge sampling result information.
6. The system for automatically calibrating a source synchronous data sampling point according to claim 4, further comprising: module M5: repeating the modules M1 to M4, and carrying out automatic calibration on the source synchronous data sampling points for a plurality of times.
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| CN104077257A (en) * | 2014-06-25 | 2014-10-01 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) based multi-channel data transmission synchronization delay measurement method and system |
| CN110635892A (en) * | 2019-10-12 | 2019-12-31 | 天津津航计算技术研究所 | Data sampling system based on synchronization 422 standard |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7076677B2 (en) * | 2002-12-30 | 2006-07-11 | Intel Corporation | Same edge strobing for source synchronous bus systems |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1825795A (en) * | 2005-02-24 | 2006-08-30 | 美国博通公司 | Network device and method for prediction of an optimal sampling phase |
| CN102257572A (en) * | 2009-01-12 | 2011-11-23 | 拉姆伯斯公司 | Mesochronous signaling system with core-clock synchronization |
| CN102522981A (en) * | 2011-12-28 | 2012-06-27 | 成都三零嘉微电子有限公司 | High-speed parallel interface circuit |
| CN104077257A (en) * | 2014-06-25 | 2014-10-01 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) based multi-channel data transmission synchronization delay measurement method and system |
| CN110635892A (en) * | 2019-10-12 | 2019-12-31 | 天津津航计算技术研究所 | Data sampling system based on synchronization 422 standard |
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