CN113552921A - Software and hardware interlocking system time synchronization method and system and electronic equipment - Google Patents
Software and hardware interlocking system time synchronization method and system and electronic equipment Download PDFInfo
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- CN113552921A CN113552921A CN202110613422.6A CN202110613422A CN113552921A CN 113552921 A CN113552921 A CN 113552921A CN 202110613422 A CN202110613422 A CN 202110613422A CN 113552921 A CN113552921 A CN 113552921A
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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Abstract
The invention discloses a software and hardware interlocking system time synchronization method, a system and electronic equipment, wherein the method comprises the following steps of S1: the RTC outputs a clock signal and a second pulse to the CPLD; step S2: the CPLD maintains a local timer; step S3: the second-level timer is +1 when corresponding to the rising edge of the second pulse, and the millisecond-level timer is set to be zero when corresponding to the rising edge of the second pulse; step S4: the CPU maintains a local timer and generates the local time of the CPU; step S5: CPU reads the register time; step S6: after the CPU reads back the register time in the confidence interval, the register time of the CPU and the register time are compared; step S7: the CPU reads the TIME information of the RTC and updates the CPU _ TIME _ CNT _ s with the read RTC second TIME. The invention can control the time synchronization in the local area network within the millisecond, sub-microsecond or even microsecond range, adopts the mode of software and hardware interlocking, and enhances the reliability.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a time synchronization technology.
Background
At present, an artificial intelligence system is rapidly developed, and multiple sensors and multiple systems are required to work cooperatively at many times, so that the problem of time synchronization of the multiple sensors or systems is involved. If time synchronization is not well done, data fusion of a plurality of sensors and systems is invalid, and related functions cannot be realized as a result.
Traditional time synchronization, such as industries of electric power, communication and the like, needs higher time synchronization precision (such as subminiature and nanosecond), generally adopts a mode of realizing message transmission and exchange through hardware (a switch, programmable logic and a PHY chip) and realizing time synchronization protocol logic (such as IEEE1588) through software, and the scheme has high cost and complex realization; for the time synchronization between multiple sensors and subsystems of the AI at present, only millisecond level is generally needed, and a low-cost and easy-to-implement scheme needs to be found to meet the requirement.
Disclosure of Invention
The invention aims to solve the technical problem of providing a software and hardware interlocking system time synchronization method, which meets the time synchronization requirement by using a scheme with low cost and easy realization.
In order to solve the technical problems, the invention adopts the following technical scheme: a system time synchronization method of software and hardware interlocking comprises the following steps:
step S1: the RTC outputs a clock signal and a second pulse to the CPLD;
step S2: the CPLD maintains a local timer CPLD _ TIME _ CNT according to an input clock signal and generates CPLD local TIME, wherein the local timer CPLD _ TIME _ CNT consists of two stages of timers which are a second-stage timer CPLD _ TIME _ CNT _ s and a millisecond-stage timer CPLD _ TIME _ CNT _ ms respectively; step S3: the second-level timer CPLD _ TIME _ CNT _ s is +1 at the rising edge of the corresponding second pulse, and the millisecond-level timer CPLD _ TIME _ CNT _ ms is set to be zero at the rising edge of the corresponding second pulse;
step S4: the CPU maintains a local timer CPU _ TIME _ CNT and generates the local TIME of the CPU, wherein the local timer CPU _ TIME _ CNT consists of two stages of timers which are a second-stage timer CPU _ TIME _ CNT _ s and a millisecond-stage timer CPU _ TIME _ CNT _ ms respectively;
step S5: the CPU reads the CPLD _ TIME _ CNT _ S and the CPLD _ TIME _ CNT _ ms register TIME, and if the read CPLD _ TIME _ CNT _ ms register TIME is within the confidence interval, the step S6 is executed; if the read CPLD _ TIME _ CNT _ ms register TIME is not within the confidence interval, delaying the set TIME, and then executing step S5 again;
step S6: after the CPU reads back the CPLD _ TIME _ CNT _ ms register TIME in the confidence interval, comparing the CPU _ TIME _ CNT _ ms register TIME with the CPLD _ TIME _ CNT _ ms register TIME, and directly jumping to the step S7 if the difference does not exceed the threshold; if the difference exceeds the threshold, assigning the CPLD _ TIME _ CNT _ ms register TIME to the CPU _ TIME _ CNT _ ms, completing the synchronous operation of the millisecond-level timer CPU _ TIME _ CNT _ ms and CPLD _ TIME _ CNT _ ms, and jumping to the step S7; step S7: the CPU reads the TIME information of the RTC and updates the CPU _ TIME _ CNT _ s by using the read RTC second TIME; if the register TIME of the CPLD _ TIME _ CNT _ S read back in the step S5 is inconsistent with the second TIME read back from the RTC, writing the RTC second TIME information into a corresponding register of the CPLD, and updating the CPLD _ TIME _ CNT _ S;
s8: through the steps, the RTC, the CPLD and the CPU realize millisecond time synchronization, and the CPLD and the CPU give time to the peripheral.
Preferably, the method further comprises the step of compensating the CPU operation delay, wherein the CPU operation delay comprises the average operation delay CPU _ RD _ CPLD _ TD for the CPU to read the CPLD; reading the average operation delay CPU _ RD _ RTC _ TD of the RTC by the CPU; the average operation of the CPU writing CPLD is delayed by CPU _ WR _ CPLD _ TD.
Preferably, the confidence interval is 50ms to 500ms, wherein 50ms is the leading edge of the confidence interval and 500ms is the trailing edge of the confidence interval.
Preferably, the first and second liquid crystal materials are,
confidence interval trailing edge + CPU _ RD _ CPLD _ TD + CPU _ RD _ RTC _ TD + CPU _ WR _ CPLD _ TD <1000 ms.
The invention also provides a system time synchronization system with software and hardware interlocking, which comprises an RTC, a CPLD and a CPU, wherein the CPU is connected with the RTC through a serial port 1, the CPU is connected with the CPLD through a serial port 2, the CPU and the CPLD are provided with time service interfaces connected with peripheral equipment, and the system time synchronization system realizes time synchronization by adopting the system time synchronization method with software and hardware interlocking.
The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the steps of the software and hardware interlocking system time synchronization method when executing the computer program.
The technical scheme adopted by the invention meets the time synchronization requirement by a scheme with low cost and easy realization through the cooperation of the CPU, the RTC, the CPLD and the software thereof, and has the following beneficial effects:
1. the time synchronization is in the range of millisecond, sub-microsecond or even microsecond, the required precision requirement can be selected according to the self requirement, the cost is low, and the realization is easy.
2. And the reliability is enhanced by adopting a software and hardware interlocking mode.
3. The external interface has strong expansibility and can be simultaneously used for the external time service of the CPU and the FPGA.
4. The time service interface mode is flexible and changeable, and is not limited to traditional internet access, GPS and the like.
5. Along with the increasing time precision of future chips, the time synchronization precision can also be continuously improved.
The following detailed description of the present invention will be provided in conjunction with the accompanying drawings.
Drawings
The invention is further described with reference to the accompanying drawings and the detailed description below:
FIG. 1 is a block diagram of a system time synchronization system with software and hardware interlocking according to the present invention;
FIG. 2 is a waveform of 1 pps;
FIG. 3 is a schematic diagram of CPLD _ TIME _ CNT _ s and CPLD _ TIME _ CNT _ ms timers being synchronized by 1pps and RTC;
FIG. 4 is a diagram of comparison between read CPLD _ TIME _ CNT _ ms and confidence interval.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following explains the relevant terms appearing in the specific embodiments of the present invention:
a CPU: a central processing unit.
RTC: real Time Clock, a common Clock chip.
CPLD: common programmable logic chips (extendable to FPGAs); by programming, the CPLD maintains a local time via a local multi-bit counter.
Peripheral 1/2: common devices such as cameras, radar, laser, etc., or various subsystems.
A serial port 1: common such as I2C, RS232, SPI, etc. (extensible to PCE, etc. interfaces); the CPU reads the real-time of the RTC through the serial port 1.
And 2, serial port 2: common such as I2C, RS232, SPI, etc. (extensible to PCE, etc. interfaces); and the CPU reads the local time of the CPLD and writes the CPLD register through the serial port 2.
1pps interface: commonly called second pulse, is an accurate 1s timing pulse; the duty cycle is flexible, here exemplified at 50%, and the waveform is shown in fig. 2.
A Clock interface: is a high frequency clock (e.g., 32khz) output by the RTC.
Example one
A system time synchronization method of software and hardware interlocking is disclosed, the scheme of the embodiment takes implementation of millisecond synchronization as an example, and comprises the following steps:
step S1: the RTC outputs a clock signal and a second pulse to the CPLD.
Step S2: the CPLD maintains a local timer CPLD _ TIME _ CNT according to an input clock signal (frequency division and frequency multiplication can be carried out according to the TIME precision requirement), and generates CPLD local TIME.
Step S3: as shown in fig. 3, the second-level timer CPLD _ TIME _ CNT _ s is set to +1 at the rising edge of the corresponding second pulse, and the millisecond-level timer CPLD _ TIME _ CNT _ ms is set to zero at the rising edge of the corresponding second pulse.
Step S4: the CPU maintains a local timer CPU _ TIME _ CNT and generates the TIME local to the CPU, and the local timer CPU _ TIME _ CNT is composed of two stages of timers, namely a second-stage timer CPU _ TIME _ CNT _ s and a millisecond-stage timer CPU _ TIME _ CNT _ ms.
Step S5: as shown in FIG. 4, the CPU reads CPLD _ TIME _ CNT _ s
And CPLD _ TIME _ CNT _ ms register TIME (when the CPU reads TIME from the CPLD, the current timing register value of the CPLD), if the read CPLD _ TIME _ CNT _ ms register TIME is within the confidence interval, executing step S6, and starting a complete timing operation;
if the read CPLD _ TIME _ CNT _ ms register TIME is not within the confidence interval, the step S5 is executed again after delaying the set TIME (ensuring that the next CPLD reading operation falls to the confidence interval of the next 1 second).
Step S6: after the CPU reads back the CPLD _ TIME _ CNT _ ms register TIME in the confidence interval, comparing the CPU _ TIME _ CNT _ ms register TIME with the CPLD _ TIME _ CNT _ ms register TIME, and directly jumping to the step S7 if the difference does not exceed the threshold; if the difference exceeds the threshold (the threshold can be determined as required, for example, 10ms), the CPLD _ TIME _ CNT _ ms register TIME is assigned to the CPU _ TIME _ CNT _ ms, the synchronous operation of the millisecond-level timers CPU _ TIME _ CNT _ ms and CPLD _ TIME _ CNT _ ms is completed, and the process goes to step S7.
Step S7: the CPU reads the TIME information of the RTC and updates the CPU _ TIME _ CNT _ s by using the read RTC second TIME; if the register TIME of the CPLD _ TIME _ CNT _ S read back in the step S5 is inconsistent with the second TIME read back from the RTC, writing the RTC second TIME information into a corresponding register of the CPLD, and updating the CPLD _ TIME _ CNT _ S; the precise synchronization of the CPLD and the RTC second time is completed through the step.
S8: through the steps, the RTC, the CPLD and the CPU realize millisecond time synchronization, and the CPLD and the CPU give time to the peripheral.
In the above steps, in order to achieve better synchronization effect, the delay of CPU operation needs to be compensated. Therefore, the method further comprises the step of compensating the CPU operation delay, wherein the CPU operation delay comprises the average operation delay CPU _ RD _ CPLD _ TD of the CPU reading CPLD; reading the average operation delay CPU _ RD _ RTC _ TD of the RTC by the CPU; the average operation of the CPU writing CPLD is delayed by CPU _ WR _ CPLD _ TD. These delays are averaged over multiple measurements and written as constants to the CPU and CPLD, which results in better time synchronization performance.
Meanwhile, the scheme of the embodiment does not consider the delay (small, neglected) of the CPU internal updating operation, including the operation delay of updating the local second timer CPU _ TIME _ CNT _ s after the CPU reads back the TIME information from the RTC, and the operation delay of updating CPU _ TIME _ CNT _ ms after the CPU reads back the TIME information from the CPLD.
It will be appreciated that the confidence interval may be determined based on actual read-write operation delay parameters. For example, in the present embodiment, the confidence interval is 50ms to 500ms, where 50ms is the leading edge of the confidence interval and 500ms is the trailing edge of the confidence interval.
It can be understood that the operation of the solution of the present embodiment is based on the following time constraints: confidence interval trailing edge + CPU _ RD _ CPLD _ TD + CPU _ RD _ RTC _ TD + CPU _ WR _ CPLD _ TD <1000 ms. Is a complete longest operation, which is completed within one second period of the CPLD.
Example two
As shown in fig. 1, a software and hardware interlocking system time synchronization system includes an RTC, a CPLD (or FPGA) and a CPU, where the RTC is provided with a Clock interface and a 1pps interface, and respectively outputs a Clock signal and a second pulse to the outside, the CPU is connected with the RTC through a serial port 1, the CPU is connected with the CPLD through a serial port 2, the CPU and the CPLD are provided with time service interfaces connected with peripheral devices, and the peripheral devices may be provided with a plurality of peripheral devices, for example, a peripheral device 1 and a peripheral device 2, and the time synchronization system implements time synchronization by using the software and hardware interlocking system time synchronization method described in the first embodiment.
EXAMPLE III
An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of a software and hardware interlocked system time synchronization method according to an embodiment when executing the computer program.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that the invention is not limited thereto, and may be embodied in other forms without departing from the spirit or essential characteristics thereof. Any modification which does not depart from the functional and structural principles of the present invention is intended to be included within the scope of the claims.
Claims (6)
1. A system time synchronization method of software and hardware interlocking is characterized by comprising the following steps:
step S1: the RTC outputs a clock signal and a second pulse to the CPLD;
step S2: the CPLD maintains a local timer CPLD _ TIME _ CNT according to an input clock signal and generates CPLD local TIME, wherein the local timer CPLD _ TIME _ CNT consists of two stages of timers which are a second-stage timer CPLD _ TIME _ CNT _ s and a millisecond-stage timer CPLD _ TIME _ CNT _ ms respectively;
step S3: the second-level timer CPLD _ TIME _ CNT _ s is +1 at the rising edge of the corresponding second pulse, and the millisecond-level timer CPLD _ TIME _ CNT _ ms is set to be zero at the rising edge of the corresponding second pulse;
step S4: the CPU maintains a local timer CPU _ TIME _ CNT and generates the local TIME of the CPU, wherein the local timer CPU _ TIME _ CNT consists of two stages of timers which are a second-stage timer CPU _ TIME _ CNT _ s and a millisecond-stage timer CPU _ TIME _ CNT _ ms respectively;
step S5: the CPU reads the CPLD _ TIME _ CNT _ S and the CPLD _ TIME _ CNT _ ms register TIME, and if the read CPLD _ TIME _ CNT _ ms register TIME is within the confidence interval, the step S6 is executed; if the read CPLD _ TIME _ CNT _ ms register TIME is not within the confidence interval, delaying the set TIME, and then executing step S5 again;
step S6: after the CPU reads back the CPLD _ TIME _ CNT _ ms register TIME in the confidence interval, comparing the CPU _ TIME _ CNT _ ms register TIME with the CPLD _ TIME _ CNT _ ms register TIME, and directly jumping to the step S7 if the difference does not exceed the threshold; if the difference exceeds the threshold, assigning the CPLD _ TIME _ CNT _ ms register TIME to the CPU _ TIME _ CNT _ ms, completing the synchronous operation of the millisecond-level timer CPU _ TIME _ CNT _ ms and CPLD _ TIME _ CNT _ ms, and jumping to the step S7;
step S7: the CPU reads the TIME information of the RTC and updates the CPU _ TIME _ CNT _ s by using the read RTC second TIME; if the register TIME of the CPLD _ TIME _ CNT _ S read back in the step S5 is inconsistent with the second TIME read back from the RTC, writing the RTC second TIME information into a corresponding register of the CPLD, and updating the CPLD _ TIME _ CNT _ S;
s8: through the steps, the RTC, the CPLD and the CPU realize millisecond time synchronization, and the CPLD and the CPU give time to the peripheral.
2. The software and hardware interlocked system time synchronization method according to claim 1, wherein: the method also comprises the step of compensating the CPU operation delay, wherein the CPU operation delay comprises the average operation delay CPU _ RD _ CPLD _ TD of the CPU reading CPLD; reading the average operation delay CPU _ RD _ RTC _ TD of the RTC by the CPU; the average operation of the CPU writing CPLD is delayed by CPU _ WR _ CPLD _ TD.
3. The software and hardware interlocked system time synchronization method according to claim 2, wherein: the confidence interval is 50 ms-500 ms, wherein 50ms is the leading edge of the confidence interval, and 500ms is the trailing edge of the confidence interval.
4. The software and hardware interlocked system time synchronization method according to claim 3, wherein: confidence interval trailing edge + CPU _ RD _ CPLD _ TD + CPU _ RD _ RTC _ TD + CPU _ WR _ CPLD _ TD <1000 ms.
5. The utility model provides a system time synchronization system of software and hardware interlocking, includes RTC, CPLD and CPU, CPU passes through serial ports 1 and is connected with RTC, CPU passes through serial ports 2 and is connected with CPLD, CPU and CPLD are equipped with the time service interface of being connected with the peripheral hardware, its characterized in that: the system time synchronization system adopts the software and hardware interlocking system time synchronization method of any one of claims 1 to 4 to realize time synchronization.
6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: the processor implements the steps of a software and hardware interlocked system time synchronization method as described in any one of 1-4 when executing the computer program.
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