CN107193205A - A kind of time memory circuit for pipeline-type time-to-digit converter - Google Patents
A kind of time memory circuit for pipeline-type time-to-digit converter Download PDFInfo
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- CN107193205A CN107193205A CN201710374780.XA CN201710374780A CN107193205A CN 107193205 A CN107193205 A CN 107193205A CN 201710374780 A CN201710374780 A CN 201710374780A CN 107193205 A CN107193205 A CN 107193205A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
A kind of time storage circuit for pipeline-type time-to-digit converter, belongs to time measurement field, in order to solve the problems, such as that existing time memory can not the less input signal in processing time interval.Three input signals of the impulse generator of the present invention are respectively Start, Stop and Initial after two delay units, output end is used as two first input for inputting OR gates, Trigger is used as the control voltage end of grid-control time delay chain as two second input signal for inputting OR gates, the output signal ends of two input OR gates；Two No. two delay units are respectively：No. two delay unit A and No. two delay unit B；No. two delay unit A input signal is SET signals；No. two delay unit A are connected with No. two delay unit B；16 No. three delay units are cascaded, and the input after series connection connects No. two delay unit B output end；Output end after series connection is the output end of the time memory circuit.Have the beneficial effect that and handled the less input signal of time interval.
Description
Technical field
The invention belongs to time measurement field.
Background technology
High-resolution time-to-digit converter has important in high-energy physics, the field such as laser ranging and accurate measurement
Application.Pipeline-type time-to-digit converter as high resolution time digital quantizer a kind of important implementation by
Extensive concern, time memory is the important component of pipeline-type time-to-digit converter, its performance is directly determined
The function and precision of time-to-digit converter, therefore design and optimization important in inhibiting for time memory.
Existing time memory can not produce corresponding pulse when input signal time interval is smaller, so as to limit
The scope of time measurement, while when quantization surplus is smaller, late-class circuit can not produce correct input signal, so that the time
Digital quantizer can not produce correct quantized result in this case, therefore, solve this problem pair of time memory
The function of perfect pipeline type time-to-digit converter and to improve its performance significant.
The content of the invention
The invention aims to solve existing time memory can not the less input signal in processing time interval ask
A kind of topic, it is proposed that time storage circuit for pipeline-type time-to-digit converter.
A kind of time memory circuit for pipeline-type time-to-digit converter of the present invention, including pulse hair
Raw device, two input OR gates, two delay units and grid-control time delay chain；
Input signal Start and input signal Stop is two rising edges, and input signal Initial is initial signal；
Input signal Start is as first input signal of impulse generator, and input signal Stop is by two delays
As second input signal of impulse generator after unit, input signal Initial is defeated as the 3rd of impulse generator
Enter signal；
The output end connection two of impulse generator inputs first input of OR gate, second input of two input OR gates
End receives input signal Trigger, and the output signal end of two input OR gates connects the control voltage end of grid-control time delay chain；
Grid-control time delay chain includes two No. two delay units and 16 No. three delay units；
The output signal end of two input OR gates simultaneously with the control voltage end of two No. two delay units and 16 No. three
The control voltage end of delay unit is connected；
Two No. two delay units are respectively：No. two delay unit A and No. two delay unit B；No. two delay unit A's is defeated
Enter signal for SET signals；No. two delay unit A output end is connected with No. two delay unit B input；
16 No. three delay units are cascaded, and the input after series connection connects No. two delay unit B output end；
Output end after series connection is the output end for the time memory circuit of pipeline-type time-to-digit converter.
The present invention operation principle be：Input signal of the impulse generator by input signal Start and after delay
Time interval between Stop is converted to pulse signal, and input signal Initial is initial signal, and pulse width is input signal
Start and input signal Stop time interval plus two delay units delay sum, the pulse signal with
Trigger signals by two input OR gates after as grid-control time delay chain control signal EN, when control signal EN be high level when,
SET signals are propagated in time delay chain, when control signal EN signals are low level, and the spread state of SET signals is kept, in control
Signal EN processed next high level continues to propagate when arriving, introduced in grid-control time delay chain two No. two extra delay units with
The error that input signal Stop is entered line delay and introduced is eliminated, definition is output as last No. three delays in grid-control time delay chain
Time difference between the output of unit and Trigger signals, then the time interval of input signal is included in output signal, so that real
The storage of time is showed.
The beneficial effects of the invention are as follows by carrying out certain delay to input signal Stop, it is ensured that impulse generator exists
Input signal time interval remains able to output pulse signal when smaller, while increasing extra two two in grid-control time delay chain
Number delay unit eliminates the error due to input signal Stop is entered line delay and introduced, so as to ensure time memory work(
Its measurement range is expanded on the basis of energy is correct；The present invention is used to may insure this level in pipeline-type time-to-digit converter
When the quantization surplus that circuit is produced is smaller, subordinate's circuit remains able to produce correct input signal, while can make time number
Word converter is measured to less time interval, improves its dynamic range.
Brief description of the drawings
Fig. 1 stores for a kind of time for pipeline-type time-to-digit converter described in specific implementation embodiment one
The circuit diagram of device circuit；
Fig. 2 is a kind of time memory circuit for pipeline-type time-to-digit converter in embodiment one
Operation principle schematic diagram；
Fig. 3 is the circuit diagram of the impulse generator in specific implementation two；
Fig. 4 is the circuit diagram of the first trigger in embodiment three.
Embodiment
Embodiment one：Illustrate present embodiment with reference to Fig. 1 and Fig. 2, one kind described in present embodiment is used to flow
The time memory circuit of pipeline type time-to-digit converter, including the input of impulse generator 1, two OR gate 2, two delays
Unit 3 and grid-control time delay chain 4；
Input signal Start and input signal Stop is two rising edges, and input signal Initial is initial signal；
Input signal Start is as first input signal of impulse generator 1, and input signal Stop is by two delays
As second input signal of impulse generator 1 after unit 3, input signal Initial is used as the 3rd of impulse generator 1
Input signal；
The output end connection two of impulse generator 1 inputs first input of OR gate 2, second of two input OR gates 2
Input receives input signal Trigger, the control voltage end of the output signal end connection grid-control time delay chain 4 of two input OR gates 2；
Grid-control time delay chain 4 includes two No. two delay units and 16 No. three delay units；
The output signal end of two input OR gates 2 simultaneously with the control voltage end of two No. two delay units and 16 No. three
The control voltage end of delay unit is connected；
Two No. two delay units are respectively：No. two delay unit A and No. two delay unit B；No. two delay unit A's is defeated
Enter signal for SET signals；No. two delay unit A output end is connected with No. two delay unit B input；
16 No. three delay units are cascaded, and the input after series connection connects No. two delay unit B output end；
Output end after series connection is the output end for the time memory circuit of pipeline-type time-to-digit converter.
In the present embodiment, 16 No. three delay units are respectively：No. three delay units are 1. to No. three delay units16 No. three delay units are cascaded, also, No. two delay unit B output end and No. three delay units are 1.
Input is connected；No. three delay unitsOutput end for this be used for pipeline-type time-to-digit converter time memory electricity
The output end on road.
Reference picture 2 illustrates the operation principle of present embodiment, and input signal Start and input signal Stop are two risings
Edge, its time is at intervals of Tin, due to delay of the input signal Stop signals by two delay units 3, so pulse is sent out
The pulse width that raw device 1 is exported is Tin+2τp, the pulse signal and input signal Trigger that impulse generator 1 is sent pass through two
The control signal EN as grid-control time delay chain 4 after OR gate 2 is inputted, in pulse width Tin+2τpInterior, SET signals will propagate Tin+2
τp；When control signal EN signals are low level, spread state is kept, when input signal Trigger high level arrives,
SET signals continue to propagate, in order to eliminate the error caused by being delayed to input signal Stop, increase in grid-control time delay chain 4
Plus two No. two extra delay units, when SET signals propagate to last No. three delay unit 16 of grid-control time delay chain 4
When, if the output signal of No. three delay units 16 is Full signals, then Full signal delay times are TFS+2τp, wherein TFSFor
The maximum delay of grid-control time delay chain 4 when not increasing extra delay unit, defines output signal ToutFor the last of grid-control time delay chain 4
Time interval between the output signal and input signal Trigger rising edges of one No. three delay unit 16, then ToutCan be with table
It is shown as：
Tout=(TFS+2τp)-(Tin+2τp)=TFS-Tin；
Time interval between the output signal and input signal Trigger rising edges of last No. three delay unit 16
The time interval between input signal Start and input signal Stop is contained, it is achieved thereby that the storage of time.
Embodiment two：Illustrate present embodiment with reference to Fig. 3, present embodiment is to described in embodiment one
A kind of time memory circuit for pipeline-type time-to-digit converter further limit, in the present embodiment, institute
Stating impulse generator 1 includes the first trigger 101, the second trigger 102 and a phase inverter 103；
Input signal Start is used as the clock end input signal of the first trigger 101, the D inputs of the first trigger 101
Connect high level；
Input signal Stop after delay is used as the clock end input signal of the second trigger 102, the second trigger
102 D input termination high level；
The reset terminal Rst of first trigger 101 is connected with the reset terminal Rst of the second trigger 102；
The reset terminal Rstn of first trigger 101 is connected with the reset terminal Rstn of the second trigger 102；
The reset terminal RstA of first trigger 101 is connected with the reset terminal RstA of the second trigger 102；
The reset terminal RstB of first trigger 101 is connected with the reset terminal RstB of the second trigger 102；
Input signal Initial simultaneously with the input of a phase inverter 103, the reset terminal Rst of the first trigger 101 and
The reset terminal Rst of second trigger 102 is connected；
The output end of a number phase inverter 103 simultaneously with the reset terminal Rstn of the first trigger 101 and the second trigger 102
Reset terminal Rstn is connected；
The output end of second trigger 102 simultaneously with the reset terminal RstB of the first trigger 101 and the second trigger 102
Reset terminal RstB is connected；
The output end of first trigger 101 simultaneously with the reset terminal RstA of the first trigger 101 and the second trigger 102
Reset terminal RstA be connected, and using the output end of the first trigger 101 as impulse generator 1 output end.
In the present embodiment, when input signal Initial is high level, the first trigger 101 and the second trigger
102 reset, and the output of the first trigger 101 and the output of the second trigger are low level；When input signal Initial is low
During level, now reset terminal Rstn is high level, when input signal Start rising edges arrive, and the first trigger 101 exports high electricity
Flat, now reset terminal RstA is high level, and when the input signal Stop after delay arrives, the second trigger 102 is exported
High level, now reset terminal RstB is high level, and the first trigger 101 and the second trigger 102 reset simultaneously, so first touches
The pulse width for sending out the output of device 101 is input signal Initial and two rising edges of input signal Stop after delay
Between time interval.
Embodiment three：Illustrate present embodiment with reference to Fig. 4, present embodiment is to described in embodiment two
A kind of time memory circuit for pipeline-type time-to-digit converter further limit, in the present embodiment,
One trigger 101 is identical with the structure of the second trigger 102, and the first trigger 101 and the second trigger 102 are that D is touched
Send out device；
First trigger 101 includes metal-oxide-semiconductor Q1-metal-oxide-semiconductor Q13, No. two phase inverters 104 and power vd D；
Power vd D positive pole is connected with the source electrode of metal-oxide-semiconductor Q1 source electrode, metal-oxide-semiconductor Q4 source electrode and metal-oxide-semiconductor Q11 simultaneously；
Metal-oxide-semiconductor Q3 source electrode, metal-oxide-semiconductor Q6 source electrode, metal-oxide-semiconductor Q9 source electrode, metal-oxide-semiconductor Q10 source electrode and metal-oxide-semiconductor Q13
Source electrode is grounded simultaneously；
Metal-oxide-semiconductor Q1 grid and D input of the metal-oxide-semiconductor Q1 grid common node as the first trigger 101；
Metal-oxide-semiconductor Q2 grid, metal-oxide-semiconductor Q4 grid, metal-oxide-semiconductor Q6 grid and metal-oxide-semiconductor Q12 grid common node conduct
The clock end of first trigger 101；
Metal-oxide-semiconductor Q7 grid as the first trigger 101 reset terminal RstA；
Metal-oxide-semiconductor Q8 grid as the first trigger 101 reset terminal RstB；
Metal-oxide-semiconductor Q9 grid as the first trigger 101 reset terminal Rstn；
Metal-oxide-semiconductor Q10 grid as the first trigger 101 reset terminal Rst；
Metal-oxide-semiconductor Q1 drain electrode is connected with metal-oxide-semiconductor Q2 source electrode；Metal-oxide-semiconductor Q2 drain electrode and metal-oxide-semiconductor Q3 drain electrode simultaneously with
Metal-oxide-semiconductor Q5 grid is connected；
Metal-oxide-semiconductor Q4 drain electrode, metal-oxide-semiconductor Q5 drain electrode, metal-oxide-semiconductor Q7 drain electrode, metal-oxide-semiconductor Q10 drain electrode and metal-oxide-semiconductor Q11
Grid is connected with metal-oxide-semiconductor Q13 grid simultaneously；
Metal-oxide-semiconductor Q5 source electrode is connected with metal-oxide-semiconductor Q6 drain electrode：
Metal-oxide-semiconductor Q7 source electrode is connected with metal-oxide-semiconductor Q8 drain electrode；
Metal-oxide-semiconductor Q8 source electrode is connected with metal-oxide-semiconductor Q9 drain electrode；
Metal-oxide-semiconductor Q12 source electrode is connected with metal-oxide-semiconductor Q13 drain electrode；
Metal-oxide-semiconductor Q11 drain electrode and metal-oxide-semiconductor Q12 drain electrode are connected with the input of No. two phase inverters 104 simultaneously；
The output end of No. two phase inverters 104 is the output end of the first trigger 101.
Embodiment four：Present embodiment is to be used for the pipeline-type time to one kind described in embodiment three
The time memory circuit of digital quantizer is further limited, in the present embodiment, metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q4 and
Metal-oxide-semiconductor Q11 is PMOS；
Metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6, metal-oxide-semiconductor Q7, metal-oxide-semiconductor Q8, metal-oxide-semiconductor Q9, metal-oxide-semiconductor Q10, metal-oxide-semiconductor Q12 and
Metal-oxide-semiconductor Q13 is NMOS tube.
Embodiment five：Present embodiment is to be used for the pipeline-type time to one kind described in embodiment one
The time memory circuit of digital quantizer is further limited, in the present embodiment, and No. two delay unit A, No. two delays are single
First B and two delay unit 3 is identical.
In the present embodiment, two delay units 3 are eliminated by No. two delay unit A and No. two delay unit B
Error caused by line delay is entered to input signal Stop.
Claims (5)
1. a kind of time memory circuit for pipeline-type time-to-digit converter, it is characterised in that including pulse generation
Device (1), two input OR gates (2), two delay units (3) and grid-control time delay chain (4)；
Input signal Start and input signal Stop is two rising edges, and input signal Initial is initial signal；
Input signal Start is as first input signal of impulse generator (1), and input signal Stop is by two delay lists
As second input signal of impulse generator (1) after first (3), input signal Initial is used as the of impulse generator (1)
Three input signals；
The output end connection two of impulse generator (1) inputs first input of OR gate (2), the second of two input OR gates (2)
Individual input receives input signal Trigger, the control of the output signal end connection grid-control time delay chain (4) of two input OR gates (2)
Voltage end；
Grid-control time delay chain (4) includes two No. two delay units and 16 No. three delay units；
The output signal end of two input OR gates (2) prolongs with the control voltage end of two No. two delay units and 16 No. three simultaneously
Shi Danyuan control voltage end is connected；
Two No. two delay units are respectively：No. two delay unit A and No. two delay unit B；No. two delay unit A input letter
Number be SET signals；No. two delay unit A output end is connected with No. two delay unit B input；
16 No. three delay units are cascaded, and the input after series connection connects No. two delay unit B output end；Series connection
Output end afterwards is the output end for the time memory circuit of pipeline-type time-to-digit converter.
2. a kind of time memory circuit for pipeline-type time-to-digit converter according to claim 1, it is special
Levy and be, the impulse generator (1) includes the first trigger (101), the second trigger (102) and a phase inverter (103)；
Input signal Start is used as the clock end input signal of the first trigger (101), the D inputs of the first trigger (101)
Connect high level；
Input signal Stop after delay is used as the clock end input signal of the second trigger (102), the second trigger
(102) D input termination high level；
The reset terminal Rst of first trigger (101) is connected with the reset terminal Rst of the second trigger (102)；
The reset terminal Rstn of first trigger (101) is connected with the reset terminal Rstn of the second trigger (102)；
The reset terminal RstA of first trigger (101) is connected with the reset terminal RstA of the second trigger (102)；
The reset terminal RstB of first trigger (101) is connected with the reset terminal RstB of the second trigger (102)；
Input signal Initial simultaneously with the input of a phase inverter (103), the reset terminal Rst of the first trigger (101) and
The reset terminal Rst of second trigger (102) is connected；
The reset terminal Rstn and the second trigger (102) of the output end of a number phase inverter (103) simultaneously with the first trigger (101)
Reset terminal Rstn be connected；
The reset terminal RstB and the second trigger (102) of the output end of second trigger (102) simultaneously with the first trigger (101)
Reset terminal RstB be connected；
The reset terminal RstA and the second trigger (102) of the output end of first trigger (101) simultaneously with the first trigger (101)
Reset terminal RstA be connected, and using the output end of the first trigger (101) as impulse generator (1) output end.
3. a kind of time memory circuit for pipeline-type time-to-digit converter according to claim 2, it is special
Levy and be, the first trigger (101) is identical with the structure of the second trigger (102), and the first trigger (101) and second is touched
It is d type flip flop to send out device (102)；
First trigger (101) includes metal-oxide-semiconductor Q1-metal-oxide-semiconductor Q13, No. two phase inverters (104) and power vd D；
Power vd D positive pole is connected with the source electrode of metal-oxide-semiconductor Q1 source electrode, metal-oxide-semiconductor Q4 source electrode and metal-oxide-semiconductor Q11 simultaneously；
Metal-oxide-semiconductor Q3 source electrode, metal-oxide-semiconductor Q6 source electrode, metal-oxide-semiconductor Q9 source electrode, metal-oxide-semiconductor Q10 source electrode and metal-oxide-semiconductor Q13 source electrode
It is grounded simultaneously；
Metal-oxide-semiconductor Q1 grid and D input of the metal-oxide-semiconductor Q3 grid common node as the first trigger (101)；
Metal-oxide-semiconductor Q2 grid, metal-oxide-semiconductor Q4 grid, metal-oxide-semiconductor Q6 grid and metal-oxide-semiconductor Q12 grid common node are used as first
The clock end of trigger (101)；
Metal-oxide-semiconductor Q7 grid as the first trigger (101) reset terminal RstA；
Metal-oxide-semiconductor Q8 grid as the first trigger (101) reset terminal RstB；
Metal-oxide-semiconductor Q9 grid as the first trigger (101) reset terminal Rstn；
Metal-oxide-semiconductor Q10 grid as the first trigger (101) reset terminal Rst；
Metal-oxide-semiconductor Q1 drain electrode is connected with metal-oxide-semiconductor Q2 source electrode；Metal-oxide-semiconductor Q2 drain electrode and metal-oxide-semiconductor Q3 drain electrode are while and metal-oxide-semiconductor
Q5 grid is connected；
Metal-oxide-semiconductor Q4 drain electrode, metal-oxide-semiconductor Q5 drain electrode, metal-oxide-semiconductor Q7 drain electrode, metal-oxide-semiconductor Q10 drain electrode and metal-oxide-semiconductor Q11 grid
It is connected simultaneously with metal-oxide-semiconductor Q13 grid；
Metal-oxide-semiconductor Q5 source electrode is connected with metal-oxide-semiconductor Q6 drain electrode：
Metal-oxide-semiconductor Q7 source electrode is connected with metal-oxide-semiconductor Q8 drain electrode；
Metal-oxide-semiconductor Q8 source electrode is connected with metal-oxide-semiconductor Q9 drain electrode；
Metal-oxide-semiconductor Q12 source electrode is connected with metal-oxide-semiconductor Q13 drain electrode；
Metal-oxide-semiconductor Q11 drain electrode and metal-oxide-semiconductor Q12 drain electrode are connected with the input of No. two phase inverters (104) simultaneously；
The output end of No. two phase inverters (104) is the output end of the first trigger (101).
4. a kind of time memory circuit for pipeline-type time-to-digit converter according to claim 3, it is special
Levy and be, metal-oxide-semiconductor Q1, metal-oxide-semiconductor Q2, metal-oxide-semiconductor Q4 and metal-oxide-semiconductor Q11 are PMOS；
Metal-oxide-semiconductor Q3, metal-oxide-semiconductor Q5, metal-oxide-semiconductor Q6, metal-oxide-semiconductor Q7, metal-oxide-semiconductor Q8, metal-oxide-semiconductor Q9, metal-oxide-semiconductor Q10, metal-oxide-semiconductor Q12 and metal-oxide-semiconductor
Q13 is NMOS tube.
5. a kind of time memory circuit for pipeline-type time-to-digit converter according to claim 1, it is special
Levy and be, No. two delay unit A, No. two delay unit B and two delay units (3) are identical.
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| CN106019923A (en) * | 2016-05-18 | 2016-10-12 | 中国科学技术大学 | FPGA-based time-to-digital converter |
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| CN101515155A (en) * | 2008-02-18 | 2009-08-26 | 瑞昱半导体股份有限公司 | Time-to-digital conversion circuit and correlation method thereof |
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