WO2020077557A1

WO2020077557A1 - Duty cycle calibration circuit, electronic device and method

Info

Publication number: WO2020077557A1
Application number: PCT/CN2018/110617
Authority: WO
Inventors: 陶婷婷; 毛懿鸿; 黄冲
Original assignee: 华为技术有限公司
Priority date: 2018-10-17
Filing date: 2018-10-17
Publication date: 2020-04-23
Also published as: CN112655151A; CN112655151B

Abstract

Provided in the present application are a duty cycle calibration circuit, an electronic device and a method, used to implement real time, bi-directional and highly accurate calibration of a duty cycle. The circuit comprises: a pre-processing circuit, used to generate a first clock signal and a second clock signal having opposite high and low levels according to an input clock signal; a delay circuit, used to delay the first clock signal so as to obtain a a first delayed signal, and to delay the second clock signal so as to obtain a second delayed signal; an edge-triggered pulse generator, used to generate an output clock signal according to a rising/falling edge of the first delayed signal and a rising/falling edge of the second delayed signal; and a duty cycle regulator, used to detect a duty cycle of the output clock signal and generate a control signal according to said duty cycle, so as to regulate the delay of the first clock signal and/or the delay of the second clock signal.

Description

Duty ratio calibration circuit, electronic equipment and method

Technical field

This application relates to the field of electronic technology, in particular to a duty cycle calibration circuit, electronic equipment and method.

Background technique

The duty cycle of the clock (Duty Cycle) is an important performance index in clock performance. Duty cycle usually refers to the ratio of the duration of a positive pulse to the pulse period in an ideal sequence of pulse cycles. For example, if the duty ratio is 50%, it means that the width of the high-level clock cycle is equal to the width of the low-level clock cycle. In the application of PLL, the 50% duty cycle input signal is helpful to reduce the output noise of the PLL system.

In the prior art, many digital phase-locked loop (PLL) reference clock frequency multiplier circuits usually calibrate the input reference clock with a 50% duty cycle, and then frequency-double the calibrated clock signal , As the reference clock of the double frequency of PLL. However, the digital calibration process in the prior art cannot realize real-time calibration, and the calibration accuracy is low.

Summary of the invention

The embodiments of the present application provide a duty cycle calibration circuit, an electronic device and a method, which are used for real-time, bidirectional and high-precision calibration of the duty cycle.

In a first aspect, a duty cycle calibration circuit is provided. The duty cycle calibration circuit includes: a preprocessing circuit, a delay circuit, an edge trigger pulse generator, and a duty cycle regulator; wherein, the preprocessing circuit is used to: The input clock signal generates a first clock signal and a second clock signal, the first clock signal is opposite to the high and low levels of the second clock signal; the delay circuit is used to delay the first clock signal to obtain the first delay signal, and delay the second The clock signal obtains the second delayed signal; this edge triggers the pulse generator to generate an output clock signal according to the rising / falling edge of the first delay signal and the rising / falling edge of the second delay signal, for example, the rising / falling edge is rising Edge or falling edge; the duty cycle regulator is used to detect the duty cycle of the output clock signal and generate a control signal according to the duty cycle to delay the first clock signal and / or the delay of the second clock signal Make adjustments.

In the above technical solution, by adjusting the delay of the first clock signal and / or the delay of the second clock signal, the duty cycle of the output clock signal generated by the edge trigger pulse generator can be reduced or increased, so by matching the duty cycle The ratio regulator detects the adjustment in real time to generate an output clock signal with a certain duty ratio, thereby realizing real-time, bidirectional and high-precision calibration of the duty ratio. The control part of the scheme is all digital circuits, so the duty cycle calibration circuit contributes limited noise while reducing system noise.

In a possible implementation manner of the first aspect, the duty cycle regulator is specifically configured to generate a control signal when the duty cycle of the output clock signal is not 50%, to control the The delay and / or the delay of the second clock signal are adjusted. In the above possible implementation manner, the duty ratio of the output clock signal can be guaranteed to be 50%.

In a possible implementation manner of the first aspect, the edge trigger pulse generator is specifically configured to: generate an output clock signal according to the rising edge of the first delay signal and the rising edge of the second delay signal, and output the pulse of the clock signal The width is equal to the width between the rising edge of the first delay signal and the rising edge of the second delay signal; or, the output clock signal is generated according to the falling edge of the first delay signal and the falling edge of the second delay signal, and the pulse of the output clock signal The width is equal to the width between the rising edge of the first delay signal and the rising edge of the second delay signal. In the foregoing possible implementation manners, several methods for generating an output clock signal according to the rising / falling edge of the first delayed signal and the rising / falling edge of the second delayed signal are provided.

In a possible implementation manner of the first aspect, the edge-triggered pulse generator includes: two pulse generators and an RS flip-flop; wherein the input ends of the two pulse generators are both coupled to the output end of the delay circuit, It is used to receive the first delay signal and the second delay signal; the output terminals of the two pulse generators are respectively coupled to the R input terminal and the S input terminal of the RS flip-flop, and the output terminal of the RS flip-flop is used to output the output clock signal. In the foregoing possible implementation manners, an edge-triggered pulse generator with a simple structure and easy implementation is provided, and the problem of mismatch between the rising and falling edges of the first delay signal and the second delay signal can be avoided.

In a possible implementation manner of the first aspect, the edge-triggered pulse generator includes: two D flip-flops, two buffers, and a NAND gate; wherein, the CP input terminals of the two D flip-flops are respectively coupled to The output terminal of the delay circuit is used to receive the first delay signal and the second delay signal, the D input terminals of the two D flip-flops are both coupled to the power supply terminal, and the output terminals of the two D flip-flops are respectively coupled to the two buffers The input terminal of the NAND gate is coupled to the reset terminals of the two D flip-flops, and the AND terminal of the NAND gate is coupled to the output terminal of the first buffer of the two buffers. The output clock signal, the other AND terminal of the NAND gate is coupled to the output terminal of the second buffer. In the foregoing possible implementation manners, an edge-triggered pulse generator with a simple structure and easy implementation is provided, and the problem of mismatch between the rising and falling edges of the first delay signal and the second delay signal can be avoided.

In a possible implementation manner of the first aspect, the delay circuit includes two delay sub-circuits, each delay sub-circuit includes: two NOT gates and a variable capacitor; wherein, the first of the two NOT gates The input terminal of each NOT gate is used to receive the first clock signal or the second clock signal. The output terminal of the first NOT gate and the input terminal of the second NOT gate are coupled to a fixed terminal of the variable capacitor. The other fixed terminal is coupled to ground. The adjustment terminal of the variable capacitor is used to adjust the capacitance value of the variable capacitor following the control signal to adjust the delay of the first clock signal or the delay of the second clock signal. The output terminal of the second NOT gate It is used to output the first delay signal or the second delay signal. In the above possible implementation manner, a delay circuit with a simple structure and easy implementation is provided, and the bidirectional and high-precision calibration of the duty ratio can be guaranteed.

In a possible implementation manner of the first aspect, the duty cycle regulator includes: a time-to-digital converter and a controller; a time-to-digital converter for detecting the duty cycle of the output clock signal; and a controller for A control signal is generated based on the duty cycle to adjust the delay of the first clock signal and / or the delay of the second clock signal. In the foregoing possible implementation manners, it is possible to ensure real-time detection of the duty cycle and real-time, bidirectional, and high-precision calibration.

In a second aspect, an electronic device is provided, the electronic device comprising: a radio frequency device and a duty cycle calibration circuit; wherein, the duty cycle calibration circuit is used to provide a carrier signal for the radio frequency device, and the duty cycle calibration circuit is as described above The duty cycle calibration circuit provided in the first aspect or any possible implementation manner of the first aspect.

In a third aspect, a method for duty cycle calibration is provided. The method includes: generating a first clock signal and a second clock signal according to an input clock signal, the first clock signal and the second clock signal having opposite high and low levels; delaying the first The clock signal obtains the first delayed signal, and the second clock signal is delayed to obtain the second delayed signal; the output clock signal is generated according to the rising / falling edge of the first delay signal and the rising / falling edge of the second delay signal, such as the rising / falling The edge includes a rising edge or a falling edge; the duty cycle of the output clock signal is detected, and a control signal is generated according to the duty cycle to adjust the delay of the first clock signal and / or the delay of the second clock signal.

In a possible implementation manner of the third aspect, generating a control signal according to the duty ratio to adjust the delay of the first clock signal and / or the delay of the second clock signal includes: when the output clock signal is detected When the duty ratio of is not 50%, a control signal is generated to adjust the delay of the first clock signal and / or the delay of the second clock signal.

In a possible implementation manner of the third aspect, generating the output clock signal according to the rising / falling edge of the first delay signal and the rising / falling edge of the second delay signal includes: according to the rising edge and the first The rising edge of the second delay signal generates an output clock signal, the pulse width of the output clock signal is equal to the width between the rising edge of the first delay signal and the rising edge of the second delay signal; or, according to the falling edge of the first delay signal and the first The falling edge of the two delay signals generates an output clock signal, and the pulse width of the output clock signal is equal to the width between the rising edge of the first delay signal and the falling edge of the second delay signal.

Understandably, the above-mentioned electronic devices or duty cycle calibration methods are used to calibrate the output clock signal in the duty cycle calibration circuit, therefore, for the beneficial effects that can be achieved, refer to the duty cycle calibration provided above The beneficial effects in the circuit will not be repeated here.

BRIEF DESCRIPTION

1 is a schematic structural diagram of a duty cycle calibration circuit provided by an embodiment of the present application;

2 is a timing diagram of a clock signal provided by an embodiment of this application;

3 is a schematic structural diagram of another duty cycle calibration circuit provided by an embodiment of the present application;

4 is a schematic structural diagram of an edge trigger pulse generator provided by an embodiment of the present application;

FIG. 5 is a schematic flowchart of a duty cycle calibration method provided by an embodiment of the present application.

detailed description

In this application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or", describing the relationship of related objects, indicating that there can be three relationships, for example, A and / or B, which can mean: A exists alone, A and B exist at the same time, B exists alone, where A, B can be singular or plural. "At least one of the following" or a similar expression refers to any combination of these items, including any combination of single items or plural items. For example, at least one (a) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c may be single or multiple. The character "/" generally indicates that the related object is a "or" relationship. In addition, in the embodiments of the present application, the words “first” and “second” do not limit the number and the execution order.

It should be noted that in the present application, the words "exemplary" or "for example" are used as examples, illustrations or explanations. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as more preferred or advantageous than other embodiments or design. Rather, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific manner. "Coupling" in the present application may be understood as a direct connection or an indirect connection. For example, A is coupled to B, which may mean that A and B are directly connected, or A and B are indirectly connected.

1 is a schematic structural diagram of a duty cycle calibration circuit provided by an embodiment of the present application. Referring to FIG. 1, the duty cycle calibration circuit includes: a preprocessing circuit 110, a delay circuit 120, an edge trigger pulse generator 130, and a duty cycle Ratio regulator 140.

The pre-processing circuit 110 is used to generate a first clock signal and a second clock signal according to the input clock signal. The first clock signal is opposite to the high and low levels of the second clock signal.

The delay circuit 120 is configured to delay the first clock signal to obtain a first delayed signal, and delay the second clock signal to obtain a second delayed signal. The delay circuit 120 may include a first delay sub-circuit 121 and a second delay sub-circuit 122. The first delay sub-circuit 121 is used to delay the first clock signal to obtain the first delay signal, and the second delay sub-circuit 122 is used to delay the first The second clock signal obtains the second delayed signal. Optionally, the first delay sub-circuit 121 is used to delay the first clock signal according to the first delay amount to obtain the first delay signal, and the second delay sub-circuit 122 is used to delay the second clock signal according to the second delay amount to obtain the second delay Signal; both the first delay amount and the second delay amount may include a fixed delay amount and an adjusted delay amount, the size of the fixed delay amount depends on the delay circuit 120 itself, the adjusted delay amount depends on the control bits and the minimum adjustment unit, the minimum adjustment unit determines The calibration accuracy of the duty cycle calibration circuit. For example, the first delay amount is expressed as td_DLR, the corresponding fixed delay amount is expressed as τ ₁ , the corresponding control bits and the minimum adjustment unit are expressed as Dcal1 and τ _res1 , then td_DLR can be expressed by the following formula (1); Expressed as td_DLS, the corresponding fixed delay is expressed as τ ₂ , the corresponding control bits and minimum adjustment unit are expressed as Dcal2 and τ _res2 , then td_DLS can be expressed by the following formula (2).

td_DLR = τ ₁ + Dcal1 · τ _res1 (1)

td_DLS = τ ₂ + Dcal2 · τ _res2 (2)

The edge trigger pulse generator 130 is used to generate an output clock signal according to the rising / falling edge of the first delay signal and the rising / falling edge of the second delay signal, and the rising / falling edge may be a rising edge or a falling edge. Optionally, the edge trigger pulse generator 130 is used to generate an output clock signal according to the rising edge of the first delay signal and the rising edge of the second delay signal, and the pulse width of the output clock signal at this time is equal to the rising edge of the first delay signal and The width between the rising edges of the second delay signal; for example, when the rising edge of the first delay signal comes, the output clock signal is pulled to a high level, when the rising edge of the second delay signal comes, the output clock signal is Becomes low, the pulse width of the output clock signal at this time (taking the pulse width corresponding to the high level as an example) depends on the width between the rising edge of the first delay signal and the rising edge of the second delay signal (you can also (Called phase difference). Alternatively, the edge trigger pulse generator 130 is used to generate an output clock signal according to the falling edge of the first delay signal and the falling edge of the second delay signal, and the pulse width of the output clock signal is equal to the falling edge of the first delay signal and the first The width between the falling edges of the two delay signals; for example, when the falling edge of the first delay signal comes, the output clock signal is pulled to a high level, when the falling edge of the second delay signal comes, the output clock signal is Becomes low, the pulse width of the output clock signal at this time (take the pulse width corresponding to the high level as an example) depends on the width between the falling edge of the first delay signal and the falling edge of the second delay signal (you can also (Called phase difference). Therefore, the duty cycle (also called pulse width) of the output clock signal depends on the sum of the pulse width of the original input clock signal and the delay difference between the first delay amount and the second delay amount, ie PW_out = PW_in + (td_DLR-td_DLS ), PW_out represents the pulse width of the output clock signal, and PW_in represents the pulse width of the original input clock signal. When increasing the first delay amount or decreasing the second delay amount, the duty ratio of the output clock signal increases, and when decreasing the first delay amount or increasing the second delay amount, the duty ratio of the output clock signal decreases.

The duty ratio adjuster 140 is used to detect the duty ratio of the output clock signal output by the edge trigger pulse generator 130 and generate a control signal according to the duty ratio to delay the first clock signal and / or the second clock The delay of the signal is adjusted. Specifically, the duty ratio adjuster 140 may be used to adjust the first delay amount and / or the second delay amount; the delay circuit 120 delays the first clock signal according to the adjusted first delay amount to obtain the first delay signal, and according to the adjustment The delayed second delay amount delays the second clock signal to obtain a second delayed signal; the edge trigger pulse generator 130 generates an output clock signal with a certain duty ratio according to the first delayed signal and the second delayed signal obtained after adjusting the delay. For example, when the duty cycle regulator 140 detects that the duty cycle of the output clock signal is not 50%, it generates a control signal to adjust the delay of the first clock signal and / or the delay of the second clock signal so that the edge The trigger pulse generator 130 generates an output clock signal with a duty ratio of 50% according to the first delay signal and the second delay signal obtained by the adjusted delay circuit 120.

It should be noted that the duty cycle of 50% may mean that the duty cycle is equal to 50%, and may have a certain fault tolerance range, for example, the fault tolerance range is ± 2%, when the duty cycle is between 48% and When it is within the range of 52%, it is considered that the duty ratio is 50%. The specific fault tolerance range can be set by a person skilled in the art, which is not specifically limited in the embodiments of the present application.

The duty ratio of the output clock signal depends on the input duty ratio and the delay difference between the first delay amount and the second delay amount, and the duty ratio adjuster 140 changes the delay difference by adjusting the first delay amount and the second delay amount To achieve the adjustment of the duty cycle of the output clock signal. Since the delay difference can be a positive value or a negative value, the duty cycle calibration circuit can realize bidirectional calibration, and the fixed delays of the first delay amount and the second delay amount can be calibrated out, so the adjustment accuracy is only It depends on the adjustment accuracy of the delay amount. Specifically, the duty ratio adjuster 140 is used to adjust the control bits corresponding to the first delay amount and / or the second delay amount, that is, the duty ratio adjuster 140 is specifically used to adjust Dcal1 and / or in the above formula (1) Dcal2 in formula (2) has nothing to do with the fixed delay amount τ ₁ corresponding to the first delay amount and the fixed delay amount τ ₂ corresponding to the second delay amount, and therefore can achieve high-accuracy duty cycle calibration.

It should be noted that in FIG. 1 above, Fin denotes the input clock signal, R0 denotes the first clock signal, S0 denotes the second clock signal, R0 denotes the first delay signal, R1 denotes the first delay signal, S1 denotes the second delay signal, and Fout Indicates the output clock signal. If the edge trigger pulse generator 130 generates the output clock signal Fout according to the rising edge of the first delay signal R1 and the rising edge of the second delay signal S1, for example, the relationship between Fin, R0, S0, R1, S1, and Fout Can be shown in Figure 2. In FIG. 2, PW_in represents the pulse width corresponding to the high level of the input clock signal, PW_out represents the pulse width corresponding to the high level of the output clock signal, PW_out = PW_in + (td_DLR-td_DLS).

In a possible implementation, as shown in FIG. 3, the preprocessing circuit 110 includes a first NOT gate 111, a second NOT gate 112, and a third NOT gate 113; the input terminal of the first NOT gate 111 and the second The input of the NOT gate 112 is coupled to receive the input clock signal; the output of the second NOT gate 112 is coupled to the input of the third NOT gate 113; the output of the first NOT gate 111 is used to output the first clock signal, The output terminal of the third NOT gate 113 is used to output a second clock signal. Among them, the first clock signal is the signal after the input clock signal undergoes the inversion process of the first NOT gate 111 (that is, the high level of the input clock signal is changed to a low level, and the low level of the input clock signal is changed to a high level) The phase of the first clock signal is opposite to the phase of the input clock signal, that is, the high and low levels of the first clock signal are opposite to the high and low levels of the input clock signal. The second clock signal is the signal of the input clock signal after being inverted by the second NOT gate 112 and the third NOT gate 113. The phase of the second clock signal is the same as the phase of the input clock signal, that is, the high and low levels of the second clock signal are The high and low levels of the input clock signal are the same, so that the high and low levels of the first clock signal are opposite to the high and low levels of the second clock signal.

It should be noted that the above-mentioned pre-processing circuit 110 shown in FIG. 3 is only exemplary, and in practical applications, the pre-processing circuit 110 can implement level inversion of the input clock signal. In addition, the preprocessing circuit 110 may also invert the input clock signal (2N + 1) times to obtain the first clock signal, and invert the input clock signal 2N times to obtain the second clock signal, where N is a non-negative integer.

In a possible implementation, as shown in FIG. 2, the first delay sub-circuit 121 includes: a first NOT gate 1211, a second NOT gate 1212, and a variable capacitor 1213; wherein, the first NOT gate 1211 Is used to receive the first clock signal. The output of the first NOT gate 1211 and the input of the second NOT gate 1212 are coupled to a fixed end of the variable capacitor 1213, and the other of the variable capacitor 1213 is fixed. The terminal is coupled to ground. The output of the second NOT gate 1212 is used to output the first delayed signal. The adjustment terminal of the variable capacitor 1213 is coupled to the duty cycle regulator 140 to adjust the capacitance of the variable capacitor 1213 following the control signal. Value to adjust the delay of the first clock signal (for example, adjust the control bit corresponding to the first delay amount). The second delay sub-circuit 122 includes: a first NOT gate 1221, a second NOT gate 1222, and a variable capacitor 1223; wherein, the input terminal of the first NOT gate 1221 is used to receive the second clock signal, and the first NOT gate The output terminal of the gate 1221 and the input terminal of the second NOT gate 1222 are both coupled to a fixed terminal of the variable capacitor 1223, the other fixed terminal of the variable capacitor 1223 is coupled to ground, and the output terminal of the second NOT gate 1222 is used to The second delay signal is output, and the adjustment terminal of the variable capacitor 1223 is coupled to the duty cycle regulator 140 for adjusting the capacitance of the variable capacitor 1223 following the control signal to adjust the delay of the second clock signal (for example, adjusting the above Control bits corresponding to the second delay amount).

It should be noted that both the variable capacitor 1213 and the variable capacitor 1223 in the embodiment of the present application may be a capacitor that satisfies the required capacitance value, or may be a plurality of capacitors connected in parallel or in series to meet the required capacitance value Capacitor combination, that is, the corresponding capacitance value after the multiple capacitors are connected in series or in parallel is equal to the required capacitance value. In addition, the first delay sub-circuit 121 and the second delay sub-circuit 122 shown in FIG. 3 are only exemplary, and do not limit the embodiment of the present application. The embodiment of the present application may also use other methods for the first delay sub-circuit 121 和第二迟子电路 122。 121 and the second delay sub-circuit 122.

In a possible implementation, as shown in FIG. 3, the edge trigger pulse generator 130 includes a first pulse generator 131, a second pulse generator 132 and an RS flip-flop 133. The input terminal of the first pulse generator 131 is coupled to the output terminal of the first delay circuit 121 for receiving the first delay signal, and the output terminal of the first pulse generator 131 is coupled to the R of the RS flip-flop 133 Input terminal; the input terminal of the second pulse generator 132 is coupled to the output terminal of the second delay circuit 122 for receiving the second delay signal, and the output terminal of the second pulse generator 132 is coupled to the S of the RS flip-flop 133 The input terminal; the output terminal of the RS flip-flop 133 is coupled to the input terminal of the duty ratio regulator 140, and is used to output the output clock signal.

Alternatively, as shown in FIG. 4, the edge trigger pulse generator 130 includes a first D flip-flop 134, a second D flip-flop 135, a first buffer 136, a second buffer 137 and a NAND gate 138. The CP input terminal of the first D flip-flop 134 is coupled to the output terminal of the first delay sub-circuit 121 for receiving the first delay signal, and the D input terminal of the first D flip-flop 134 is coupled to the power supply terminal VDD, The output of the first D flip-flop 134 is coupled to the input of the first buffer 136; the CP input of the second D flip-flop 135 is coupled to the output of the second delay sub-circuit 122 for receiving the second delay Signal, the D input terminal of the second D flip-flop 135 is coupled to the power supply terminal VDD, the output terminal of the second D flip-flop 135 is coupled to the input terminal of the second buffer 137; the non-terminals of the NAND gate 138 are respectively coupled to The reset terminal RST of the first D flip-flop 134 and the reset terminal RST of the second D flip-flop 135; an AND terminal of the NAND gate 138 is coupled to the output terminal of the first buffer 134 for outputting the output clock The signal, the other AND terminal of the NAND gate 138 is coupled to the output terminal of the second buffer 135. Among them, the reset terminal RST of the first D flip-flop 134 and the reset terminal RST of the second D flip-flop 135 can be reset by a high level, or can be reset at the same level.

In a possible implementation manner, as shown in FIG. 3, the duty ratio regulator 140 includes a time-to-digital converter (TDC) 141 and a controller 142. The input terminal of the time-to-digital converter 141 is coupled to the output terminal of the edge-triggered pulse generator 130 to receive the output clock signal generated by the edge-triggered pulse generator 130; the output terminal of the time-to-digital converter 141 and the controller 142 The input terminals are coupled, and the output terminals of the controller are respectively coupled to the first delay sub-circuit 121 and the second delay sub-circuit 122 for adjusting the delay of the first clock signal and / or the delay of the second clock signal. Specifically, the time-to-digital converter 141 is used to perform phase comparison between the phase-locked loop feedback clock signal and the output clock signal of the frequency multiplier 150, and the duty cycle information of the output clock signal (Fout) can be reflected in the output of the TDC 141; The controller 142 is used to generate a control signal according to the duty ratio to adjust the delay of the first clock signal and / or the delay of the second clock signal. Optionally, the controller 142 is used to adjust the control bit Dcal1 corresponding to the first delay amount and / or the control bit Dcal2 corresponding to the second delay amount when the duty cycle of the output clock signal is not 50%, so that the edge triggers The pulse generator 130 generates an output clock signal with a duty ratio of 50%.

Further, as shown in FIG. 3, the duty cycle calibration circuit may further include: a frequency multiplier 150 coupled between the edge trigger pulse generator 130 and the duty cycle regulator 140, which is used for the edge trigger pulse generator The output clock signal generated by 130 is subjected to frequency multiplication processing, and the output clock signal after frequency multiplication processing is transmitted to the duty ratio regulator 140.

In the embodiment of the present application, the duty ratio adjuster 140 can detect the duty ratio of the output clock signal output by the trigger pulse generator 130 in real time, and adjust the delay of the first clock signal and / or the Delay can reduce the duty cycle of the output clock signal or increase the duty cycle of the output clock signal, which can generate a certain duty cycle of the output clock signal, for example, the edge trigger pulse generator 130 generates a duty cycle of 50% Output clock signal, thus realizing real-time, bidirectional and high-precision calibration of the duty cycle, while reducing system noise.

An embodiment of the present application further provides a terminal. The terminal includes at least a radio frequency device and a duty cycle calibration circuit provided by the embodiment of the present application. The duty cycle calibration circuit is used to provide a local carrier signal for the radio frequency device. The radio frequency device is used in any one or combination of the following: a cellular mobile communication module, a Bluetooth module, a wireless fidelity (WiFi) module in the terminal, or any device that requires a local carrier signal. For example, the radio frequency device in the terminal may be a Bluetooth module and a WiFi module, and may also be a Bluetooth module or a WiFi module.

An embodiment of the present application further provides a base station. The base station includes at least a transceiver and a phase-locked loop circuit. The phase-locked loop circuit includes a duty cycle calibration circuit provided in an embodiment of the present application. The duty cycle calibration circuit is used to The base station's transceiver provides local carrier signals.

It should be noted that the above-mentioned terminal and base station are only examples of products that apply the duty cycle calibration circuit provided by the embodiments of the present application, and cannot constitute a restriction on the application of the duty cycle calibration circuit provided by the embodiments of the present application. The provided duty cycle calibration circuit can be applied to any scene that requires duty cycle calibration, and any product that requires duty cycle calibration.

FIG. 5 is a schematic flowchart of a duty cycle calibration method provided by an embodiment of the present application, which is applied to an electronic device including a duty cycle calibration circuit provided by an embodiment of the present application. Referring to FIG. 5, the method includes the following steps .

S501: Generate a first clock signal and a second clock signal according to the input clock signal. The first clock signal and the second clock signal have opposite high and low levels.

S502: Delay the first clock signal to obtain a first delayed signal, and delay the second clock signal to obtain a second delayed signal.

S503: Generate an output clock signal according to the rising / falling edge of the first delayed signal and the rising / falling edge of the second delayed signal, and the rising / falling edge may be a rising edge or a falling edge. Optionally, the output clock signal is generated according to the rising edge of the first delay signal and the rising edge of the second delay signal; or, the output clock signal is generated according to the falling edge of the first delay signal and the falling edge of the second delay signal.

S504: Detect the duty ratio of the output clock signal, and generate a control signal according to the duty ratio to adjust the delay of the first clock signal and / or the delay of the second clock signal. Optionally, when the duty cycle of the output clock signal is detected to be not 50%, a control signal is generated to adjust the delay of the first clock signal and / or the delay of the second clock signal, for example, by adjusting the implementation of the above device In the example, control bits corresponding to the first delay amount and / or the second delay amount. After adjusting the delay of the first clock signal and / or the delay of the second clock signal, it may return to S502 to continue execution until it is detected that an output clock signal with a duty ratio of 50% is generated in S503.

It should be noted that, for the specific description of each step in the above method embodiment, reference may be made to the description of related devices or circuits in the embodiment corresponding to the above duty cycle calibration circuit, which will not be repeated in the embodiments of the present application.

In the embodiment of the present application, by adjusting the delay of the first clock signal and / or the delay of the second clock signal, the duty cycle of the output clock signal can be reduced or the duty cycle of the output clock signal can be increased, so by detecting this The duty cycle and adjustment can generate a certain duty cycle output clock signal, thereby realizing the real-time, bidirectional and high-precision calibration of the duty cycle, and the system noise is low.

The above are only specific implementations of the present application, but the scope of protection of the present application is not limited thereto, and the scope of protection of the present application shall be subject to the scope of protection of the claims.

Claims

A duty cycle calibration circuit, characterized in that the circuit includes: a preprocessing circuit, a delay circuit, an edge trigger pulse generator, and a duty cycle regulator;

The preprocessing circuit is configured to generate a first clock signal and a second clock signal according to the input clock signal, and the first clock signal is opposite to the high and low levels of the second clock signal;

The delay circuit is configured to delay the first clock signal to obtain a first delayed signal, and delay the second clock signal to obtain a second delayed signal;

The edge trigger pulse generator is configured to generate an output clock signal according to the rising / falling edge of the first delay signal and the rising / falling edge of the second delay signal;

The duty cycle regulator is configured to detect the duty cycle of the output clock signal and generate a control signal according to the duty cycle to delay the first clock signal and / or the second clock The delay of the signal is adjusted.
The calibration circuit according to claim 1, wherein the duty cycle regulator is specifically used for:

When it is detected that the duty cycle of the output clock signal is not 50%, a control signal is generated to adjust the delay of the first clock signal and / or the delay of the second clock signal.
The calibration circuit according to claim 1 or 2, wherein the edge-triggered pulse generator is specifically used to:

The output clock signal is generated according to the rising edge of the first delay signal and the rising edge of the second delay signal, and the pulse width of the output clock signal is equal to the rising edge of the first delay signal and the second The width between the rising edges of the delayed signal; or,

The output clock signal is generated according to the falling edge of the first delay signal and the falling edge of the second delay signal, and the pulse width of the output clock signal is equal to the falling edge of the first delay signal and the first The width between the rising edges of the two delayed signals.
The calibration circuit according to any one of claims 1-3, wherein the edge-triggered pulse generator includes: two pulse generators and an RS trigger;

Wherein, the input ends of the two pulse generators are both coupled to the output end of the delay circuit, and are used to receive the first delay signal and the second delay signal; the output ends of the two pulse generators They are respectively coupled to the R input end and the S input end of the RS flip-flop, and the output end of the RS flip-flop is used to output the output clock signal.
The calibration circuit according to any one of claims 1-3, wherein the edge trigger pulse generator includes: two D flip-flops, two buffers, and a NAND gate;

Wherein, the CP input terminals of the two D flip-flops are respectively used to receive the first delay signal and the second delay signal, and the D input terminals of the two D flip-flops are both coupled to the power supply terminal, the The output ends of the two D flip-flops are respectively coupled to the input ends of the two buffers, the non-ends of the NAND gates are respectively coupled to the reset ends of the two D flip-flops, one of the NAND gates The AND terminal is coupled to the output terminal of the first buffer of the two buffers for outputting the output clock signal, and the other AND terminal of the NAND gate is coupled to the output terminal of the second buffer .
The calibration circuit according to any one of claims 1 to 5, wherein the delay circuit includes two delay sub-circuits, and each delay sub-circuit includes: two NOT gates and a variable capacitor;

The input terminal of the first NOT gate of the two NOT gates is used to receive the first clock signal or the second clock signal, and the output terminal of the first NOT gate is connected to the second NOT gate The input terminal of the gate is coupled to one fixed terminal of the variable capacitor, the other fixed terminal of the variable capacitor is coupled to ground, and the adjustment terminal of the variable capacitor is used to adjust the variable capacitor following the control signal To adjust the delay of the first clock signal or the delay of the second clock signal, the output terminal of the second NOT gate is used to output the first delay signal or the second delay signal .
The calibration circuit according to any one of claims 1-6, wherein the duty cycle regulator includes: a time-to-digital converter and a controller;

The time-to-digital converter is used to detect the duty cycle of the output clock signal;

The controller is configured to generate a control signal according to the duty ratio to adjust the delay of the first clock signal and / or the delay of the second clock signal.
An electronic device, characterized in that the electronic device includes: a radio frequency device and a duty cycle calibration circuit; wherein, the duty cycle calibration circuit is used to provide a carrier signal for the radio frequency device, and the duty cycle calibration A circuit as claimed in any one of claims 1-7.
A duty cycle calibration method, characterized in that the method includes:

Generating a first clock signal and a second clock signal according to the input clock signal, the first clock signal being opposite to the high and low levels of the second clock signal;

Delaying the first clock signal to obtain a first delayed signal, and delaying the second clock signal to obtain a second delayed signal;

Generating an output clock signal according to the rising / falling edge of the first delayed signal and the rising / falling edge of the second delayed signal;

Detecting the duty cycle of the output clock signal and generating a control signal according to the duty cycle to adjust the delay of the first clock signal and / or the delay of the second clock signal.
The method according to claim 9, wherein the generating a control signal according to the duty ratio to adjust the delay of the first clock signal and / or the delay of the second clock signal includes :

When it is detected that the duty cycle of the output clock signal is not 50%, a control signal is generated to adjust the delay of the first clock signal and / or the delay of the second clock signal.
The method according to claim 9 or 10, wherein the generating an output clock signal according to the rising / falling edge of the first delayed signal and the rising / falling edge of the second delayed signal includes:

The output clock signal is generated according to the rising edge of the first delay signal and the rising edge of the second delay signal, and the pulse width of the output clock signal is equal to the rising edge of the first delay signal and the second The width between the rising edges of the delayed signal; or,

The output clock signal is generated according to the falling edge of the first delay signal and the falling edge of the second delay signal, and the pulse width of the output clock signal is equal to the falling edge of the first delay signal and the first The width between the rising edges of the two delayed signals.