CN109039310A - The method and device of adaptive adjustment phase place delay - Google Patents
The method and device of adaptive adjustment phase place delay Download PDFInfo
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- CN109039310A CN109039310A CN201710437084.9A CN201710437084A CN109039310A CN 109039310 A CN109039310 A CN 109039310A CN 201710437084 A CN201710437084 A CN 201710437084A CN 109039310 A CN109039310 A CN 109039310A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
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Abstract
The embodiment of the present invention provides a kind of method and device of adaptive adjustment phase place delay.The method and device, it can be by the scheduled retardation of designed, designed institute since according to different interface features, and utilize the reference delay chain having with a delay chain same design, to obtain and the scheduled flux matched required step number of delay, and after practical step number of this known delay chain during operation, according to this two step numbers purpose difference, to decide whether to adjust the practical step number of this delay chain.
Description
Technical field
The present invention relates to a kind of method and devices of adaptive adjustment phase place delay, and can be used for height more particularly to one kind
In fast interface circuit, the method and device of adaptive adjustment phase place delay.
Background technique
With the progress of the communication technology, the rate that information sends and receives then tends to faster.This has also required must have more
The stabilizing clock circuit of high-frequency and higher precision realizes the transmission and recovery (reception) of data.However, in actual operation,
Since by the influence of processing procedure, voltage and temperature (process, voltage and temperature, PVT), high-frequency clock
Phase may change with different operating conditions, and then influence information transmit-receive correctness.In order to solve clock phase
Usually delay chain (Delay Line) can be arranged in transceiver interface to adjust clock in the problem of position changes under various operating conditions
Phase.The technical principle of delay chain is the phase for adjusting the original clock synchronous with data (Clock), make its generate with
Phase difference between former input clock, that is, input data, to confirm the correctness of data sampling.Therefore, one kind how is provided to be used for
In high-speed interface circuit, the method and device of adaptive adjustment phase place delay is really the problem of fields urgent need to resolve.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of method and device of adaptive adjustment phase place delay, and especially
Being related to one kind can be used in high-speed interface circuit, the method and device of adaptive adjustment phase place delay.
The embodiment of the present invention provides a kind of method of adaptive adjustment phase place delay.The step of the method, is as follows.Firstly,
A step-length with reference to delay chain is calculated by a reference clock, wherein this has identical with a delay chain with reference to delay chain
Component.Secondly, setting one target value, and according to the ratio relation of this target value and step-length calculate this with reference to delay chain it is enabled
When a default step number.Then, obtain this delay chain it is enabled after at least one practical step number, and according to this reality
Border step number and default step number purpose difference, to decide whether to adjust this practical step number.
The embodiment of the present invention separately provides a kind of device of adaptive adjustment phase place delay.Described device includes one first capture
Circuit, one second capture circuit and a tracking circuit.First capture circuit, one is calculated by a reference clock with reference to delay
One step-length of chain, wherein this has component identical with a delay chain with reference to delay chain.Second capture circuit is then to set one
Target value, and this default step number with reference to delay chain when enabled is calculated according to the ratio relation of this target value and step-length
Mesh.Tracking circuit then to obtain this delay chain it is enabled after at least one practical step number, and according to this practical step
Number and default step number purpose difference, to decide whether to adjust this practical step number.
In conclusion the method and device of adaptive adjustment phase place delay provided by the embodiment of the present invention, can be and borrow
By the scheduled retardation (also that is, target value) of designed, designed institute since according to different interface features, and using having and prolong
The reference delay chain of slow chain same design, to obtain with the scheduled flux matched required step number of delay (also that is, default step
Order mesh), and after practical step number of the known delay chain during operation, it is (also that is, practical according to this two steps number
Step number and default step number) difference, to decide whether to adjust practical step number of the delay chain during operation.
Be further understood that feature and technology contents of the invention to be enabled, please refer to below in connection with it is of the invention specifically
Bright and attached drawing, but these explanations are intended merely to illustrate the present invention with attached drawing, rather than interest field of the invention is made any
Limitation.
Detailed description of the invention
Figure 1A is the schematic diagram of delay chain provided by the embodiment of the present invention.
Figure 1B is time sequences figure of the delay chain of Figure 1A under a preferred embodiment.
Fig. 2 is the flow diagram of the method for adaptive adjustment phase place delay provided by the embodiment of the present invention.
Fig. 3 is the flow diagram for calculating the step-length with reference to delay chain in the method for Fig. 2 by reference to clock.
Fig. 4 is the schematic diagram for forming self-maintained circuit provided by the embodiment of the present invention with reference to delay chain.
Fig. 5 be obtained in the method for Fig. 2 delay chain it is enabled after practical step number, and according to practical step number
With default step number purpose difference, to decide whether to adjust practical step number purpose flow diagram.
Fig. 6 is the function box schematic diagram of the device of adaptive adjustment phase place delay provided by the embodiment of the present invention.
Specific embodiment
Hereinafter, it will illustrate that the present invention various embodiments carry out the present invention is described in detail by schema.However, of the invention
Concept may embody in many different forms, and should not be construed as limited by exemplary embodiments set forth herein.In addition,
Same reference numbers can be used to indicate similar component in the drawings.
Specifically, the method and device of adaptive adjustment phase place delay provided by the embodiment of the present invention, can be suitable
For in any high-speed interface circuit.In other words, the present invention is not intended to limit the specific implementation of high-speed interface circuit, this skill
Relevant design should can be carried out according to actual demand or application by having usually intellectual in art field.In addition, according to the prior art
It is found that a delay chain can be used, then in high-speed interface circuit to be used to input signal (or can be referred to as clock signal)
Carry out scheduled delay.
For example, Figure 1A is please referred to, Figure 1A is the schematic diagram of delay chain provided by the embodiment of the present invention.Such as Figure 1A institute
Show, delay chain 11 is made of 4 concatenated delay cells 111~114.Delay cell 111~114 of the present embodiment are
Quantity is only first used to be illustrated for 4 example, but it is not intended to limiting the invention.In other embodiments, delay chain
It can also be connected and be formed by the delay cell of other quantity, such as 2,16, or even 32 etc..
In addition, in the ideal case, each delay cell 111~114 is all made of same design, so each delay cell
111~114 ductile steps, then be all configured to identical number.That is, each delay cell 111~114 all has
An identical maximum step number stages_num (not being painted).Furthermore aforementioned each step number all has an equal step
Long △ (not being painted), therefore the maximum delay amount τ that each delay cell 111~114 can be provided out, can be expressed as calculating
Shown in formula (1).
τ=stages_num* △ formula (1)
As an example it is assumed that in the case where each delay cell 111~114 may provide maximum delay amount τ, when
Delay chain 11 receives an input signal X0When, output signal Y that each delay cell 111~114 provides respectivelyi(also that is, i is
1~4 any positive integer), then it can be sequentially gap length τ having the same, as shown in Figure 1B.That is, output signal
Y4It at most can be with input signal X0Time delay with 4* τ.In addition, by adjusting the ductile step number of each delay cell
Mesh can adjust output signal Y on demandiWith input signal X0Time delay length.Since the operation principles of delay chain 11 have been
Have known by usually intellectual in the art, therefore is dissolved in the thin portion in relation to above-mentioned each delay cell 111~114
This just no longer adds to repeat.
It should be noted that may need to be designed using different delays, therefore due to different interface features in existing skill
In art, delay chain 11 is can be according at least one control signal (not being painted) received and to control each delay cell respectively
Retardation provided by 111~114, so that its output signal can generate scheduled phase difference with input signal, to solve background
The problem of clock signal phase deviates in technology.However, although at present pulse capture mode can be dependent on to calibrate the mistake mostly
Difference, but pulse capture mode can bring a large amount of circuit and power consumption simultaneously.It therefore, is this please refer to Fig. 2, Fig. 2
The flow diagram of the method for adaptive adjustment phase place delay provided by inventive embodiments.
Firstly, in step s 200, a step-length with reference to delay chain is calculated by a reference clock, wherein this is referred to
Delay chain has component identical with delay chain 11.Secondly, setting a target value, and according to this target in step S210
The ratio relation of value and step-length calculates this default step number with reference to delay chain when enabled.Then, in step S220,
At least one practical step number after acquirement delay chain 11 is enabled, and according to this practical step number and default step number
Difference, to decide whether to adjust this practical step number.
Teaching according to the above, the usually intellectual of having should be appreciated that in the art, the embodiment of the present invention
The delay of adaptive adjustment phase place method, can be entirely that but can be connect according to different different from existing technological means
The scheduled retardation (also that is, target value) of designed, designed institute since mouth characteristic, and utilization has and 11 same design of delay chain
Reference delay chain, with obtain with the scheduled flux matched required step number of delay (also that is, default step number), and
After practical step number of the known delay chain 11 during operation, according to this two steps number (also that is, practical step number with
Default step number) difference, to decide whether to adjust practical step number of the delay chain 11 during operation.
Below in order to further explain the realization details about step S200, the present invention further provides its step S200
A kind of embodiment.Referring to Fig. 3, Fig. 3 is the step-length calculated by reference to clock in the method for Fig. 2 with reference to delay chain
Flow diagram.It is worth noting that, the embodiment of following uses is only to illustrate, not to limit this hair herein
It is bright.In addition, the part process step identical as Fig. 2 is indicated in Fig. 3 with identical figure number, therefore no longer add to be described in detail it herein carefully
Section.
As shown in figure 3, more may include having step S300~step S310 in step S200.Firstly, in step S300, this
After embodiment can will add a reverser with reference to delay chain to form a self-maintained circuit, and recycle this self-maintained circuit
Voluntarily to generate reference clock.Wherein, a period of this reference clock is then equal to this total delay with reference to possessed by delay chain
2 times of time.Then, in step s310, a counter is triggered using this reference clock, and when one section of statistics fixed
Between after, according to a count value of counter, to calculate the period of this reference clock, and obtain this refer to delay chain step-length.
Specifically, Fig. 4 is with reference to delay chain provided by the embodiment of the present invention to form self-excitation please refer to Fig. 4
The schematic diagram of oscillating circuit.As described in previous contents, since reference delay chain 13 has design identical with delay chain 11, because
This is equally to be made of multiple concatenated 131~13M of delay cell with reference to delay chain 13.Wherein, in order to cooperate Fig. 1 to say
It is bright, thus the 131~13M of delay cell of the present embodiment be then also use quantity for 4 example come be illustrated (also that is, delay
Unit 131~134), but it is not intended to limiting the invention.
In addition, then also all configuration contains identical maximum step number stages_num to each delay cell 131~134,
And each step number all has equal step-length △.It is understood, therefore, that institute is calculated on reference delay chain 13
Step number (also that is, default step number) can directly be covered among delay chain 11.It should be noted that according to existing skill
Art it is found that each delay cell 131~134,111~114 maximum step number stages_num, being can be according to being relevant to
It is determined with reference to the precision of delay chain 13 and delay chain 11.In other words, the present invention is not intended to limit maximum step number stages_
The specific implementation of num, the usually intellectual of having should can carry out correlation according to actual demand or application in the art
Design.
On the other hand, it should be appreciated that assuming that in the uncertain step-length △ feelings with reference to delay chain 13 (or delay chain 11)
Under condition, will with reference to delay chain 13 plus reverser 15 to form self-maintained circuit after, just can self-oscillation produce a reference
Clock Ref_clk, as shown in Figure 4.However, being had since the period of reference clock Ref_clk is then equal to reference to delay chain 13
2 times of total delay time Total_Delay (not being painted), therefore remove flip-flop number 17 using reference clock Ref_clk, and
And after counting one section of set time, just reference clock can be known come counter push back by the count value (not being painted) of counter 17
The period of Ref_clk, so that it is determined that with reference to the step-length △ of delay chain 13 (or delay chain 11).
For example, in the present embodiment, with reference to the total delay time Total_Delay of delay chain 13, that is, it is represented by
Shown in following formula (2).
Total_Delay=τ * delaychain_num formula (2)
=(stages_num* △ * delaychain_num)
Wherein, delaychain_num is then the total number of these delay cells 131~134.
However, in order to clearly calculate the above-mentioned total delay time with reference to delay chain 13, therefore the present embodiment is available another
One counter 18, and count the counter 18 with a fixed frequency.For example, in the present embodiment, just
Can to fixed frequency Fix_clk be 125M hertz (Hz) mode come make counter 18 counting.
That is, the time interval that counter 18 counts every time is 8 nanoseconds.Then, with control signal (not being painted)
Start counter 18 and counter 17 simultaneously.It therefore, is 2 when the set time in above-mentioned statistics20Overturn clock time (invert
Clock time), and when terminating the count value of counter 18 after statistics and being then represented as f125_cnt_num, institute in step S300
The formula for calculating the period of reference clock Ref_clk can be expressed as shown in formula (3).
(stages_num*△*delaychain_num)*2*220=f125_cnt_num*8 formula (3)
According to previous contents it is found that the total number delaychain_num of these delay cells 131~134, is use
The example that quantity is 4 is illustrated (also that is, delaychain_num=4).In addition, in order to facilitate following explanation, this implementation
The maximum step number stages_num of example is then to be adopted as 32 example to be illustrated (also that is, stages_num=32),
But it is not intended to limiting the invention.
Therefore, according to above-mentioned parameter it is found that formula (3) just can be further simplified to shown in following formula (4), but this hair
It is bright to be also not limited system.
(32*△*4)*2*220=f125_cnt_num*8 formula (4)
Then, in step S300 the acquired step-length △ with reference to delay chain 13 formula, formula (5) can be expressed as
It is shown.
It should be noted that in formula (5) step-length △ unit, can equally be expressed as nanosecond.Additionally, it should be appreciated that
It is, it is so-called in step S210 " target value ", it also also refers to be intended to control so that via pre- caused by reference delay chain 13
Fixed delay.
Therefore, when the step-length △ with reference to delay chain 13 has been determined, the embodiment of the present invention just can be according to the target value
With the ratio relation of step-length △, with the step number that obtains to set when enabled with reference to the institute of delay chain 13 (also that is, default walk
Order mesh).
In a kind of wherein application, the unit of target value for example can equally be expressed as nanosecond.Therefore, target value and step-length
The ratio relation of △ can be simplified shown as shown in following formula (6).
N* △=TargetDelay formula (6)
Wherein, N is default step number, and TargetDelay is then target value.
As an example it is assumed that also meaning that in the case where target value TargetDelay is set as 4, the embodiment of the present invention is
Want to control so that via reference delay chain 13 output signal, can more than input signal 4 nanoseconds of predetermined delay.Cause
This, when calculated step-length △ is 0.1 nanosecond, with reference to delay chain 13 it is enabled when and the step number that need to set, also
Being to be 40 (also that is, default △=4/0.1 step number N=TargetDelay/).
It or is that in other application, when considering further that quantization concept, target value TargetDelay can also be such as
Expression is a certain actual delay time (nanosecond) multiplied by 224.Therefore, formula (6) can also be expressed as shown in formula (7), but
It is also non-to limit the present invention.
Similarly, it should be appreciated that by the teaching of formula (5) it is found that formula (7) just can further be simplified to calculate as follows
Shown in formula (8).It should be noted that the specific implementation of above-mentioned target value TargetDelay is all merely citing herein,
It is not intended to limit the invention.
In addition, as described in previous contents, since reference delay chain 13 has design identical with delay chain 11,
With reference to the technical principle for calculating default step number N on delay chain 13, it can also refer to and be successfully acquired in delay chain
The step number that need to be set before starting to enable is intended on 11.In other words, delay chain 11 is intended to need to set before starting to enable
Step number, also can equally be expressed as on reference delay chain 13 the calculated default step number N of institute.
However, the practical step number after delay chain 11 is enabled is (for example, N because being influenced by PVTreal), then can
It is easier to have the generation of error (also that is, N with above-mentioned default step number Nreal≠N).Therefore, in step S220, when this
Embodiment obtained delay chain 11 it is enabled after practical step number NrealAfterwards, the present embodiment just can be further according to this practical step
Rank number NrealWith the difference of default step number N, to decide whether to adjust practical step number Nreal。
As an example it is assumed that in the case where above-mentioned default step number N is 40, when the reality arrived acquired in step S220
Border step number NrealWhen being then 38, the present embodiment just can to increase in a manner of the step number purpose that delay chain 11 has been set,
Practical step number N is adjusted wherebyreal.Similarly, when the practical step number N arrived acquired in step S220realIt is then 42
When, the present embodiment just can be to reduce in a manner of the step number purpose that delay chain 11 has been set, to adjust practical step number whereby
Nreal.To sum up, the above-mentioned practical step number N of adjustmentrealSpecific implementation herein all be merely citing, not use
To limit the present invention.
However, teaching according to the above, the usually intellectual of having be should be appreciated that in the art, step S220
One of main spirits be to be, successfully track delay chain 11 it is enabled after practical step number Nreal.Due to
Track delay chain 11 it is enabled after practical step number NrealOperation principles be in the art have usual knowledge
Known by person, therefore this is dissolved in related above-mentioned thin portion and just no longer adds to repeat.
Then, below in order to further explain the realization details about step S220, the present invention further provides its steps
A kind of embodiment of rapid S220.Be please refer to Fig. 5, Fig. 5 Fig. 2 method in obtain delay chain it is enabled after practical step
Order mesh, and according to practical step number and default step number purpose difference, to decide whether to adjust practical step number purpose
Flow diagram.It is worth noting that, the embodiment of following uses is only to illustrate, not to limit this hair herein
It is bright.In addition, the part process step identical as Fig. 2 is indicated in Fig. 5 with identical figure number, therefore no longer add to be described in detail it herein carefully
Section.
As shown in figure 5, more may include having step S500 in step S220.In step S500, the present embodiment, which then calculates, to be prolonged
Practical step number N after slow chain 11 is enabled in a preset timerealAn average value (for example, Navg), and according to this
Average value NavgWith the difference of default step number N, to decide whether to adjust practical step number Nreal.It should be noted that this
Invention be not intended to limit above-mentioned computing relay chain 11 it is enabled after specific implementation in a preset time, in the art
Tool usually intellectual should can carry out relevant design according to actual demand or application.
Specifically, in the embodiment of Fig. 5, this method can obtain slow chain 11 it is enabled after it is more in a preset time
A practical step number is (for example, Nreal(1)~Nreal(K), wherein K is the positive integer for being more than or equal to 2).Then, according to these
Practical step number Nreal(1)~Nreal(K), an average value N can be countedavg(also that is, Navg=(Nreal(1)+Nreal
(2)+....+Nreal(K))/K), and according to this average value NavgWith the difference of default step number N, our rule can be with certainly
It is fixed whether to adjust practical step number Nreal(K+1).For example, as average value NavgIt is greater than with the difference of default step number N
When one tolerance value, then practical step number N is adjustedreal(K+1).When above-mentioned difference is less than or equal to above-mentioned tolerance value, then not
Adjust practical step number Nreal(K+1)。
Similarly, according to this average value NavgWith the difference of default step number N, to decide whether to adjust practical step number
Mesh Nreal(K+1) detailed process then just can no longer be added to repeat such as the mode described in previous embodiment in this.It is total and
Yan Zhi, the above-mentioned practical step number N of adjustmentreal(K+1) specific implementation is also merely citing herein, not to limit
The system present invention.
Finally, in order to further explain about adaptive adjustment phase place delay method operation workflow, the present invention into
One step provides a kind of embodiment of its method.Referring to Fig. 6, Fig. 6 is adaptively to adjust phase provided by the embodiment of the present invention
The function box schematic diagram of the device of position delay.It is worth noting that, following apparatus 6 is only that the one of of the above method realizes
Mode, it is not intended to limiting the invention.
Then use has a delay to the device 6 suitable for any high-speed interface circuit, and in this high-speed interface circuit
Chain, to be used to carry out scheduled delay to input signal.It is noted that delay chain described in this example, then it can be such as aforementioned reality
Delay chain 11 described in example is applied, therefore is understood also referring to Fig. 1 with benefit.
Specifically, the device 6 may include the first capture circuit 611, second capture circuit 613 and tracking circuit
615.Wherein, above-mentioned each component, which can be through pure hardware circuit, realizes, or through hardware circuit collocation firmware or soft
Part is realized, to sum up, the present invention is not intended to limit the specific implementation of device 6.In addition, above-mentioned each component can be integration
Or it is provided separately, and the present invention is also not limited system.
More carefully to say, the first capture circuit 611 calculates a step-length with reference to delay chain by a reference clock, wherein
This has component identical with delay chain 11 with reference to delay chain.In addition, second capture circuit 613 then to set a target value,
And this default step number with reference to delay chain when enabled is calculated according to the ratio relation of this target value and step-length.Again
Person, tracking circuit 615 then postpone at least one practical step number after chain warp 11 enables to obtain, and according to this practical step
Order mesh and default step number purpose difference, to decide whether to adjust this practical step number.
It is worth noting that, the first capture circuit 611 described in this example may be to execute flow and method shown in Fig. 3, with
Calculate the step-length for referring to delay chain.In addition, reference delay chain described in this example, then it also can be such as the reference described in previous embodiment
Delay chain 13, therefore understood also referring to Fig. 3 and Fig. 4 with benefit, just no longer add that its details is described in detail in this.Similarly, this example
The tracking circuit 615 is then also likely to be to execute flow and method shown in fig. 5, to decide whether to adjust practical step number,
Therefore understood also referring to Fig. 5 with benefit, just no longer add that its details is described in detail in this.
In conclusion the method and device of adaptive adjustment phase place delay provided by the embodiment of the present invention, it can be complete
Be be different from existing technological means, but can according to different interface features since the scheduled retardation (example of designed, designed institute
Such as, 4 nanosecond), and using the reference delay chain having with delay chain same design, it is flux matched with the scheduled delay to obtain
Required step number (also that is, default step number), and after practical step number of the known delay chain during operation,
According to the difference of this two steps number (also that is, practical step number and default step number), to decide whether to adjust delay chain
Practical step number during operation.
The above, the only preferred embodiments of the disclosure, however feature of the invention is not limited thereto, this
The technical staff in field within the field of the present invention, can think easily and variation or modification, can all cover in the claims
In.
Claims (12)
1. a kind of method of adaptive adjustment phase place delay, which is characterized in that this method comprises:
A step-length with reference to delay chain is calculated by a reference clock, wherein this has and a delay chain phase with reference to delay chain
Same component；
Set a target value, and according to a ratio relation of the target value and the step-length calculate this it is enabled with reference to delay chain when
A default step number；And
Obtain the delay chain it is enabled after at least one practical step number, and according to the practical step number and the default step
One difference of order purpose, to decide whether to adjust the practical step number.
2. the method as described in claim 1, which is characterized in that wherein calculating this by the reference clock with reference to delay chain
The step-length the step of in, further includes:
This is added into a reverser with reference to delay chain to form a self-maintained circuit, and is voluntarily given birth to using the self-maintained circuit
At the reference clock, wherein a period of the reference clock is then equal to the 2 of a total delay time with reference to possessed by delay chain
Times；And
A counter is triggered using the reference clock, and after counting one section of set time, according to a meter of the counter
Numerical value to calculate the period of the reference clock, and obtains the step-length for referring to delay chain.
3. method according to claim 2, which is characterized in that wherein the delay chain and this with reference to delay chain be respectively by multiple
Concatenated delay cell is formed, and each of the delay cell is all configured containing identical one maximum step number, and
Then foundation is relevant to the delay chain to the maximum step number and the precision for referring to delay chain is determined.
4. method as claimed in claim 3, which is characterized in that wherein the total delay time for referring to delay chain is
Stages_num* △ * delaychain_num, wherein stages_num is maximum step of each of the delay cell
Number, and △ is the step-length for referring to delay chain, delaychain_num is then a total number of the delay cell.
5. method as claimed in claim 4, which is characterized in that wherein the ratio relation of the target value and the step-length is N* △
=TargetDelay, wherein N is the default step number, and TargetDelay is then the target value.
6. the method as described in claim 1, which is characterized in that wherein obtain the delay chain it is enabled after the practical step
Number, and according to the practical step number and the default step number purpose difference, to decide whether to adjust the practical step
In the step of number, further includes:
Calculate the delay chain it is enabled after practical one average value of step number purpose in a preset time, and it is flat according to this
Mean value and the default step number purpose difference, to decide whether to adjust the practical step number.
7. a kind of device of adaptive adjustment phase place delay, which is characterized in that the device includes:
One first capture circuit, a step-length with reference to delay chain is calculated by a reference clock, wherein this refers to delay chain
With component identical with a delay chain；
One second capture circuit is calculated to set a target value, and according to a ratio relation of the target value and the step-length
This with reference to delay chain it is enabled when a default step number；And
One tracking circuit, to obtain the delay chain it is enabled after at least one practical step number, and according to the practical step
Order mesh and default one difference of step number purpose, to decide whether to adjust the practical step number.
8. device as claimed in claim 7, which is characterized in that wherein the first capture circuit executes following steps to calculate this
With reference to the step-length of delay chain:
This is added into a reverser with reference to delay chain to form a self-maintained circuit, and is voluntarily given birth to using the self-maintained circuit
At the reference clock, wherein a period of the reference clock is equal to 2 times of a total delay time with reference to possessed by delay chain；
And
A counter is triggered using the reference clock, and after counting one section of set time, according to a meter of the counter
Numerical value to calculate the period of the reference clock, and obtains the step-length for referring to delay chain.
9. device as claimed in claim 8, which is characterized in that wherein the delay chain and this with reference to delay chain be respectively by multiple
Concatenated delay cell is formed, and each of the delay cell is all configured containing identical one maximum step number, and
Then foundation is relevant to the delay chain to the maximum step number and the precision for referring to delay chain is determined.
10. device as claimed in claim 9, which is characterized in that wherein the total delay time for referring to delay chain is
Stages_num* △ * delaychain_num, wherein stages_num is maximum step of each of the delay cell
Number, and △ is the step-length for referring to delay chain, delaychain_num is then a total number of the delay cell.
11. device as claimed in claim 10, which is characterized in that wherein the ratio relation of the target value and the step-length is N*
△=TargetDelay, wherein N is the default step number, and TargetDelay is the target value.
12. device as claimed in claim 7, which is characterized in that wherein the tracking circuit executes following steps to decide whether
Adjust the practical step number:
Calculate the delay chain it is enabled after practical one average value of step number purpose in a preset time, and it is flat according to this
Mean value and the default step number purpose difference, to decide whether to adjust the practical step number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710437084.9A CN109039310B (en) | 2017-06-09 | 2017-06-09 | Method and device for adaptively adjusting phase delay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710437084.9A CN109039310B (en) | 2017-06-09 | 2017-06-09 | Method and device for adaptively adjusting phase delay |
Publications (2)
| Publication Number | Publication Date |
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| CN109039310A true CN109039310A (en) | 2018-12-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116185132A (en) * | 2023-03-07 | 2023-05-30 | 矩阵时光数字科技有限公司 | Method and system for generating clock signal by self-oscillation in FPGA |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5252867A (en) * | 1992-02-14 | 1993-10-12 | Vlsi Technology, Inc. | Self-compensating digital delay semiconductor device with selectable output delays and method therefor |
| US5900762A (en) * | 1997-08-05 | 1999-05-04 | Hewlett-Packard Company | Self-calibrating electronic programmable delay line utilizing an interpolation algorithm |
| US20090322397A1 (en) * | 2007-06-15 | 2009-12-31 | Chang-Po Ma | Delay circuit and related method thereof |
| CN103378826A (en) * | 2012-04-11 | 2013-10-30 | 飞思卡尔半导体公司 | High precision single edge capture and delay measurement circuit |
| CN103427798A (en) * | 2013-08-21 | 2013-12-04 | 电子科技大学 | Multiphase clock generation circuit |
| CN105158591A (en) * | 2014-06-04 | 2015-12-16 | 领特贝特林共有限责任两合公司 | Probabilistic digital delay measurement device |
-
2017
- 2017-06-09 CN CN201710437084.9A patent/CN109039310B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5252867A (en) * | 1992-02-14 | 1993-10-12 | Vlsi Technology, Inc. | Self-compensating digital delay semiconductor device with selectable output delays and method therefor |
| US5900762A (en) * | 1997-08-05 | 1999-05-04 | Hewlett-Packard Company | Self-calibrating electronic programmable delay line utilizing an interpolation algorithm |
| US20090322397A1 (en) * | 2007-06-15 | 2009-12-31 | Chang-Po Ma | Delay circuit and related method thereof |
| CN103378826A (en) * | 2012-04-11 | 2013-10-30 | 飞思卡尔半导体公司 | High precision single edge capture and delay measurement circuit |
| CN103427798A (en) * | 2013-08-21 | 2013-12-04 | 电子科技大学 | Multiphase clock generation circuit |
| CN105158591A (en) * | 2014-06-04 | 2015-12-16 | 领特贝特林共有限责任两合公司 | Probabilistic digital delay measurement device |
Non-Patent Citations (2)
| Title |
|---|
| DAVID FICK等: ""In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter"", 《2010 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC)》 * |
| 沈奇: ""量子通信中的精密时间测量技术研究"", 《中国优秀博硕士学位论文全文数据库(博士) 信息科技辑》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116185132A (en) * | 2023-03-07 | 2023-05-30 | 矩阵时光数字科技有限公司 | Method and system for generating clock signal by self-oscillation in FPGA |
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