JPS5523667A - Counter circuit - Google Patents
Counter circuitInfo
- Publication number
- JPS5523667A JPS5523667A JP9690678A JP9690678A JPS5523667A JP S5523667 A JPS5523667 A JP S5523667A JP 9690678 A JP9690678 A JP 9690678A JP 9690678 A JP9690678 A JP 9690678A JP S5523667 A JPS5523667 A JP S5523667A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- digit
- carry
- output signal
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
- H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors
Landscapes
- Logic Circuits (AREA)
Abstract
PURPOSE:To reduce the number of wires for carry and the number of FET's, by forming the carry signal delivery line in the series connection of transfer gates which are conductive when the output signal of each digit except the most significant bit of the binary count value is at logical value 1. CONSTITUTION:When the output signal 1a in one digit is at logical value 1, the transfer gate 1g of half carry is conducted, and when the clock signal beta is at high level, the carry signal of the logic value 1 is fed to the second digit. The second digit inverts and makes the output signal 2a as the logic 1 only when the signal 1a is at 1 and every time when the clock signal a is at logical value 1. When the signals 1a and 2a are both logical 1, the gates 1g and 2g are conducted and the carry signal is fed to the next digit when the signal beta is at high level. Similarly, the operation is made to the n digit 4 to perform binary counter operation. Thus, the number of carry Tr and the number of wires can remarkably be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9690678A JPS5523667A (en) | 1978-08-08 | 1978-08-08 | Counter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9690678A JPS5523667A (en) | 1978-08-08 | 1978-08-08 | Counter circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5523667A true JPS5523667A (en) | 1980-02-20 |
JPS639411B2 JPS639411B2 (en) | 1988-02-29 |
Family
ID=14177400
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9690678A Granted JPS5523667A (en) | 1978-08-08 | 1978-08-08 | Counter circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5523667A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5873242A (en) * | 1981-10-27 | 1983-05-02 | Nec Corp | Counter circuit |
JPH044433U (en) * | 1990-04-26 | 1992-01-16 |
-
1978
- 1978-08-08 JP JP9690678A patent/JPS5523667A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5873242A (en) * | 1981-10-27 | 1983-05-02 | Nec Corp | Counter circuit |
JPH0142531B2 (en) * | 1981-10-27 | 1989-09-13 | Nippon Electric Co | |
JPH044433U (en) * | 1990-04-26 | 1992-01-16 |
Also Published As
Publication number | Publication date |
---|---|
JPS639411B2 (en) | 1988-02-29 |
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