JPS57123727A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS57123727A
JPS57123727A JP810181A JP810181A JPS57123727A JP S57123727 A JPS57123727 A JP S57123727A JP 810181 A JP810181 A JP 810181A JP 810181 A JP810181 A JP 810181A JP S57123727 A JPS57123727 A JP S57123727A
Authority
JP
Japan
Prior art keywords
counter
presetting
digits
encoder
accordance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP810181A
Other languages
Japanese (ja)
Inventor
Yoshiaki Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP810181A priority Critical patent/JPS57123727A/en
Publication of JPS57123727A publication Critical patent/JPS57123727A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Landscapes

  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To set delay time easily and optionally with high precision by adding a simple presetting circuit to a counter and by increasing the number of digits of an encoder in the presetting circuit as well as the number of digits of this counter. CONSTITUTION:To a counter 1, a 7-3 encoder 3 which performs code conversion for presetting is added, and an FF7 is set by an input signal 11 to input its negative logic output signal 29 to a changeover switch 5, thus obtaining an output signal 13 by expanding the input signal in accordance with the preset state of the switch 5. The delay time is set in accordance with the counting of a clock signal 45, so the setting has high precision.
JP810181A 1981-01-23 1981-01-23 Delay circuit Pending JPS57123727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP810181A JPS57123727A (en) 1981-01-23 1981-01-23 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP810181A JPS57123727A (en) 1981-01-23 1981-01-23 Delay circuit

Publications (1)

Publication Number Publication Date
JPS57123727A true JPS57123727A (en) 1982-08-02

Family

ID=11683904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP810181A Pending JPS57123727A (en) 1981-01-23 1981-01-23 Delay circuit

Country Status (1)

Country Link
JP (1) JPS57123727A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6087678A (en) * 1983-10-20 1985-05-17 Toshiba Corp Control circuit for inverter
JPS6285514A (en) * 1985-10-11 1987-04-20 Advantest Corp Timing signal generating device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6087678A (en) * 1983-10-20 1985-05-17 Toshiba Corp Control circuit for inverter
JPS6285514A (en) * 1985-10-11 1987-04-20 Advantest Corp Timing signal generating device
JPH0710042B2 (en) * 1985-10-11 1995-02-01 株式会社アドバンテスト Timing signal generator

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