JPH044433U - - Google Patents
Info
- Publication number
- JPH044433U JPH044433U JP4622790U JP4622790U JPH044433U JP H044433 U JPH044433 U JP H044433U JP 4622790 U JP4622790 U JP 4622790U JP 4622790 U JP4622790 U JP 4622790U JP H044433 U JPH044433 U JP H044433U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- output signal
- circuit
- counter circuit
- signal obtained
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Microcomputers (AREA)
Description
第１図は本考案回路を示す回路図、第２図は従
来回路を示す回路図、第３図は第１図及び第２図
に使用されるクロツクφ１φ２を示すタイミング
チヤートである。
４……ラツチ回路、６，１７……トランスフア
ゲート、７，８……インバータ、９……抵抗、１
０……ＡＮＤゲート。
FIG. 1 is a circuit diagram showing the circuit of the present invention, FIG. 2 is a circuit diagram showing a conventional circuit, and FIG. 3 is a timing chart showing clocks φ 1 φ 2 used in FIGS. 1 and 2. 4... Latch circuit, 6, 17... Transfer gate, 7, 8... Inverter, 9... Resistor, 1
0...AND gate.
Claims (1)
ウンすることによつて、所定ビツトの計数値を形
成するカウンタ回路において、 第１のクロツクのタイミングでラツチ動作を行
うラツチ回路と、 前段下位ビツトからのキヤリーの発生期間中ゲ
ートを開き、前記ラツチ回路の出力端子から得ら
れた出力信号を通過させる第１のトランスフアゲ
ートと、 第２のクロツクのタイミングでゲートを開き、
前記第１のトランスフアゲートの出力信号を通過
させる第２のトランスフアゲートと、 前記第２のトランスフアゲートから得られた出
力信号を保持すると共に前記ラツチ回路の入力端
子に反転印加する保持回路と、 前記前段下位ビツトからのキヤリーと前記ラツ
チ回路の反転出力端子から得られた出力信号との
論理積演算を行い、論理積演算結果を後段上位ビ
ツトへのキヤリーとする論理積ゲートと、を、 計数値の各ビツトに応じて設けたことを特徴と
するカウンタ回路。 (2) 計数値の最下位ビツトに応じて設けた構成
において、第１のトランスフアゲートは、ラツチ
回路の出力端子から得られた出力信号を常時通過
させる状態であり、且つ、論理積ゲートは、ラツ
チ回路の反転出力端子から得られた出力信号を常
時通過させる状態であり、計数値の最上位ビツト
に応じて設けた構成において、論理積ゲートは、
不要であることを特徴とする請求項(1)記載のカ
ウンタ回路。 (3) １チツプのマイクロコンピユータに集積化
することを特徴とする請求項(1)記載のカウンタ
回路。[Scope of Claim for Utility Model Registration] (1) A latch circuit that performs a latch operation at the timing of a first clock in a counter circuit that forms a count value of a predetermined bit by counting up or down a clock; a first transfer gate that opens the gate during the period in which a carry is generated from the lower bit of the previous stage and allows the output signal obtained from the output terminal of the latch circuit to pass; and a second gate that opens the gate at the timing of a second clock;
a second transfer gate that passes the output signal of the first transfer gate; a holding circuit that holds the output signal obtained from the second transfer gate and inverts and applies it to the input terminal of the latch circuit; an AND gate that performs an AND operation between the carry from the lower bit of the previous stage and the output signal obtained from the inverted output terminal of the latch circuit, and uses the result of the AND operation as the carry for the upper bit of the latter stage; A counter circuit is provided according to each bit of the counter circuit. (2) In the configuration provided according to the least significant bit of the count value, the first transfer gate is in a state of always passing the output signal obtained from the output terminal of the latch circuit, and the AND gate is In a configuration in which the output signal obtained from the inverting output terminal of the latch circuit is always passed through, and is provided according to the most significant bit of the count value, the AND gate is
2. The counter circuit according to claim 1, wherein the counter circuit is unnecessary. (3) The counter circuit according to claim (1), wherein the counter circuit is integrated into a one-chip microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990046227U JP2568104Y2 (en) | 1990-04-26 | 1990-04-26 | Counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990046227U JP2568104Y2 (en) | 1990-04-26 | 1990-04-26 | Counter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH044433U true JPH044433U (en) | 1992-01-16 |
| JP2568104Y2 JP2568104Y2 (en) | 1998-04-08 |
Family
ID=31561123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990046227U Expired - Lifetime JP2568104Y2 (en) | 1990-04-26 | 1990-04-26 | Counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2568104Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5041460A (en) * | 1973-08-17 | 1975-04-15 | ||
| JPS5523667A (en) * | 1978-08-08 | 1980-02-20 | Mitsubishi Electric Corp | Counter circuit |
-
1990
- 1990-04-26 JP JP1990046227U patent/JP2568104Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5041460A (en) * | 1973-08-17 | 1975-04-15 | ||
| JPS5523667A (en) * | 1978-08-08 | 1980-02-20 | Mitsubishi Electric Corp | Counter circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2568104Y2 (en) | 1998-04-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |