JPS5499556A - Malfunction preventing circuit for up-down counter - Google Patents

Malfunction preventing circuit for up-down counter

Info

Publication number
JPS5499556A
JPS5499556A JP605378A JP605378A JPS5499556A JP S5499556 A JPS5499556 A JP S5499556A JP 605378 A JP605378 A JP 605378A JP 605378 A JP605378 A JP 605378A JP S5499556 A JPS5499556 A JP S5499556A
Authority
JP
Japan
Prior art keywords
signal
digit
change
output
gamma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP605378A
Other languages
Japanese (ja)
Other versions
JPS6235290B2 (en
Inventor
Katsumi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP605378A priority Critical patent/JPS5499556A/en
Publication of JPS5499556A publication Critical patent/JPS5499556A/en
Publication of JPS6235290B2 publication Critical patent/JPS6235290B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation

Landscapes

  • Processing Of Color Television Signals (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To prevent the malfunction caused by introduction of the unnecessary pulse when the switching signal is applied by introducing the up-down switching signal plus the output of digit-up and digit-down signals and providing the inhibition circuit to control the digit-up and digit-down signal gate circuit. CONSTITUTION:The low-and high-order counters consist of shift registers 1-3 and 4-6. And the outpu of digit-up and digit-down signal generating NOR gates 7 and 8 are referred to as alpha and beta, and the output of FF in the inhibition circuit is gamma. When the up-down switching signal is switched to up from down thrugh terminal 19 at the generation of the digit-up signal, one input of gate 22 is O and signal gamma is O since signal beta is 1. And clock signal CK2 from digit up-down signal gate circuit 9 has no change, so output Q21-Q23 of the high-order counter has no change with no malfunction caused. When the up-down switching signal changes from up to down at the generation of digit-down signal alpha, signal alpha is 1 and signal gamma has no change (1). And no change is caused to output terminals Q21-Q23, causing no malfunction.
JP605378A 1978-01-23 1978-01-23 Malfunction preventing circuit for up-down counter Granted JPS5499556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP605378A JPS5499556A (en) 1978-01-23 1978-01-23 Malfunction preventing circuit for up-down counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP605378A JPS5499556A (en) 1978-01-23 1978-01-23 Malfunction preventing circuit for up-down counter

Publications (2)

Publication Number Publication Date
JPS5499556A true JPS5499556A (en) 1979-08-06
JPS6235290B2 JPS6235290B2 (en) 1987-07-31

Family

ID=11627865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP605378A Granted JPS5499556A (en) 1978-01-23 1978-01-23 Malfunction preventing circuit for up-down counter

Country Status (1)

Country Link
JP (1) JPS5499556A (en)

Also Published As

Publication number Publication date
JPS6235290B2 (en) 1987-07-31

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