JPS56107385A - Memory device - Google Patents

Memory device

Info

Publication number
JPS56107385A
JPS56107385A JP907180A JP907180A JPS56107385A JP S56107385 A JPS56107385 A JP S56107385A JP 907180 A JP907180 A JP 907180A JP 907180 A JP907180 A JP 907180A JP S56107385 A JPS56107385 A JP S56107385A
Authority
JP
Japan
Prior art keywords
write
readout
signal
output lines
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP907180A
Other languages
Japanese (ja)
Other versions
JPS6049998B2 (en
Inventor
Manabu Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55009071A priority Critical patent/JPS6049998B2/en
Publication of JPS56107385A publication Critical patent/JPS56107385A/en
Publication of JPS6049998B2 publication Critical patent/JPS6049998B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make faster the operating speed of memory device, by decreasing the potential difference of two output lines of the sense circuit at write-in through the use of a transistor. CONSTITUTION:A transistor Q15 is connected to two output lines RB and -RB of the voltage sense circuit, and a signal W0 which is controlled with a signal turning on Q15 at high level at write-in and turning off at low level at readout, is fed to the gate. At write-in, the write-in circuit 10 gives the complement data to the write-in base WB, -WB according to the signal W0 based on the input Din. On the other hand, the level difference of output lines RB and -RB is decreased than the level difference at readout with Q15 turned on with the signal W0. Thus, when control is moved from the write-in readout, the time t0 required to invert RB, -RB is rather faster than the case when the previous cycle is the readout cycle.
JP55009071A 1980-01-29 1980-01-29 memory device Expired JPS6049998B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55009071A JPS6049998B2 (en) 1980-01-29 1980-01-29 memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55009071A JPS6049998B2 (en) 1980-01-29 1980-01-29 memory device

Publications (2)

Publication Number Publication Date
JPS56107385A true JPS56107385A (en) 1981-08-26
JPS6049998B2 JPS6049998B2 (en) 1985-11-06

Family

ID=11710369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55009071A Expired JPS6049998B2 (en) 1980-01-29 1980-01-29 memory device

Country Status (1)

Country Link
JP (1) JPS6049998B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028096A (en) * 1983-07-27 1985-02-13 Hitachi Ltd Static ram
EP0182194A2 (en) * 1984-11-05 1986-05-28 Kabushiki Kaisha Toshiba Data output circuit for a dynamic memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028096A (en) * 1983-07-27 1985-02-13 Hitachi Ltd Static ram
EP0182194A2 (en) * 1984-11-05 1986-05-28 Kabushiki Kaisha Toshiba Data output circuit for a dynamic memory
US4719595A (en) * 1984-11-05 1988-01-12 Kabushiki Kaisha Toshiba Data output circuit for a dynamic memory

Also Published As

Publication number Publication date
JPS6049998B2 (en) 1985-11-06

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