JPS57138091A - Peripheral circuit system for non-volatile insulation gate semiconductor memory - Google Patents

Peripheral circuit system for non-volatile insulation gate semiconductor memory

Info

Publication number
JPS57138091A
JPS57138091A JP56162289A JP16228981A JPS57138091A JP S57138091 A JPS57138091 A JP S57138091A JP 56162289 A JP56162289 A JP 56162289A JP 16228981 A JP16228981 A JP 16228981A JP S57138091 A JPS57138091 A JP S57138091A
Authority
JP
Japan
Prior art keywords
write
power consumption
readout
read
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56162289A
Other languages
Japanese (ja)
Other versions
JPS5812679B2 (en
Inventor
Michitoku Kamatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56162289A priority Critical patent/JPS5812679B2/en
Publication of JPS57138091A publication Critical patent/JPS57138091A/en
Publication of JPS5812679B2 publication Critical patent/JPS5812679B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Read Only Memory (AREA)

Abstract

PURPOSE:To increase readout/write-in speed through the reduction in power consumption at write with a simple constitution, by separating the power supply for readout and write-in via load transistors with different resistance value. CONSTITUTION:MOS transistors (TRs) Ta, Tb forming write/read loads connected with write/read power supplies, in which the source and the gate are respectively grounded or isolated, are connected to an input MOSTRTc and the TRs Ta, Tb turn on according to write/read. When the resistor of the TRs Ta, Tb is taken greater for the TRTb, the power consumption at write is small, and the write which calls for less power consumption substantially can be done without fail with a consecutive application of the write-in power supply voltage of a small power consumption. On the other hand, at readout, the power consumption is increased and high speed readout is made, allowing to increase read/write speed through the reduction of power consumption at write with a simple constitution.
JP56162289A 1981-10-12 1981-10-12 Peripheral circuit system for non-volatile insulated gate semiconductor memory Expired JPS5812679B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56162289A JPS5812679B2 (en) 1981-10-12 1981-10-12 Peripheral circuit system for non-volatile insulated gate semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56162289A JPS5812679B2 (en) 1981-10-12 1981-10-12 Peripheral circuit system for non-volatile insulated gate semiconductor memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3860775A Division JPS51114037A (en) 1975-04-01 1975-04-01 A peripheral circuit design for fixed insulation-gate semiconductor me mories

Publications (2)

Publication Number Publication Date
JPS57138091A true JPS57138091A (en) 1982-08-26
JPS5812679B2 JPS5812679B2 (en) 1983-03-09

Family

ID=15751649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56162289A Expired JPS5812679B2 (en) 1981-10-12 1981-10-12 Peripheral circuit system for non-volatile insulated gate semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5812679B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952497A (en) * 1982-09-17 1984-03-27 Nec Corp Decoder circuit
US4754167A (en) * 1985-04-04 1988-06-28 Cecil Conkle Programmable reference voltage generator for a read only memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952497A (en) * 1982-09-17 1984-03-27 Nec Corp Decoder circuit
JPS6314437B2 (en) * 1982-09-17 1988-03-30 Nippon Electric Co
US4754167A (en) * 1985-04-04 1988-06-28 Cecil Conkle Programmable reference voltage generator for a read only memory

Also Published As

Publication number Publication date
JPS5812679B2 (en) 1983-03-09

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