JPS5686527A - Data latch circuit - Google Patents

Data latch circuit

Info

Publication number
JPS5686527A
JPS5686527A JP16426979A JP16426979A JPS5686527A JP S5686527 A JPS5686527 A JP S5686527A JP 16426979 A JP16426979 A JP 16426979A JP 16426979 A JP16426979 A JP 16426979A JP S5686527 A JPS5686527 A JP S5686527A
Authority
JP
Japan
Prior art keywords
level
circuit
signal phi
output
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16426979A
Other languages
Japanese (ja)
Inventor
Kazuo Tokushige
Hideo Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16426979A priority Critical patent/JPS5686527A/en
Publication of JPS5686527A publication Critical patent/JPS5686527A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356086—Bistable circuits with additional means for controlling the main nodes
    • H03K3/356095—Bistable circuits with additional means for controlling the main nodes with synchronous operation
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
    • F02P5/00—Advancing or retarding ignition; Control therefor
    • F02P5/04—Advancing or retarding ignition; Control therefor automatically, as a function of the working conditions of the engine or vehicle or of the atmospheric conditions
    • F02P5/145—Advancing or retarding ignition; Control therefor automatically, as a function of the working conditions of the engine or vehicle or of the atmospheric conditions using electrical means
    • F02P5/15—Digital data processing
    • F02P5/152—Digital data processing dependent on pinking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/10—Internal combustion engine [ICE] based vehicles
    • Y02T10/40—Engine management systems

Abstract

PURPOSE:To enable high speed operation without malfunction, by charging the gate of load MOSFET of a flip-flop circuit at the start of circuit operation, and inputting the output of two gate terminals of the load FET to a push-pull circuit after the start of operation. CONSTITUTION:The flip-flop circuit upper than dotted lines is precharged when the driving signal phi is at low level and the signal phi' is at high level, and the output nodes 18, 19 are at high level. When the input DIN of ''1'' level is fed, the circuit starts operation. Next, when the signal phi is at high level, the node 18 is at ground potential and the node 19 is at higher level with the bootstrap effect. When this level change is delivered to the push-pull circuit lower than the dotted lines, the state of low level keeps at the output terminal 40 and the level is increased for other output terminal 41. Further, since the nodes 19 and 39 are increased to the precharge level or more due to the bootstrap effect, the charging speed of the terminal 41 is faster.
JP16426979A 1979-12-18 1979-12-18 Data latch circuit Pending JPS5686527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16426979A JPS5686527A (en) 1979-12-18 1979-12-18 Data latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16426979A JPS5686527A (en) 1979-12-18 1979-12-18 Data latch circuit

Publications (1)

Publication Number Publication Date
JPS5686527A true JPS5686527A (en) 1981-07-14

Family

ID=15789872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16426979A Pending JPS5686527A (en) 1979-12-18 1979-12-18 Data latch circuit

Country Status (1)

Country Link
JP (1) JPS5686527A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6445237B2 (en) 2000-02-04 2002-09-03 Nec Corporation Flip-flop circuit
WO2003063355A1 (en) * 2002-01-24 2003-07-31 Infineon Technologies Ag Integrated circuit and circuit arrangement for converting a single-rail signal to a dual-rail signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6445237B2 (en) 2000-02-04 2002-09-03 Nec Corporation Flip-flop circuit
WO2003063355A1 (en) * 2002-01-24 2003-07-31 Infineon Technologies Ag Integrated circuit and circuit arrangement for converting a single-rail signal to a dual-rail signal
US6946878B2 (en) 2002-01-24 2005-09-20 Infineon Technologies Ag Integrated circuit and circuit arrangement for converting a single-rail signal into a dual-rail signal

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