JPS54148365A - Buffer circuit - Google Patents

Buffer circuit

Info

Publication number
JPS54148365A
JPS54148365A JP5693478A JP5693478A JPS54148365A JP S54148365 A JPS54148365 A JP S54148365A JP 5693478 A JP5693478 A JP 5693478A JP 5693478 A JP5693478 A JP 5693478A JP S54148365 A JPS54148365 A JP S54148365A
Authority
JP
Japan
Prior art keywords
gate
terminal
input
fet4
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5693478A
Other languages
Japanese (ja)
Other versions
JPS5846090B2 (en
Inventor
Kenji Anami
Osamu Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP53056934A priority Critical patent/JPS5846090B2/en
Publication of JPS54148365A publication Critical patent/JPS54148365A/en
Publication of JPS5846090B2 publication Critical patent/JPS5846090B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Abstract

PURPOSE:To reduce the power consumption by inserting the differential circuit into the connection route of the output or input terminal of the pre-inverter step and the gate terminal of depletion-type MOSFET. CONSTITUTION:When the input signal of terminal 5 changes from L to H, the gate of enhancement-type MOSFET2 becomes H with increment of the conductance. The gate of depletion-type FET4 is identical to the earth potential via resistance 13 before the input signal enters. When the input varies to H, the output of pre-inverter 20, i.e., the input of differential circuit 20 changes with the negative pulse caused at node 14. Accordingly, the gate of FET4 features the negative potential with the conductance reduced greatly. Thus, the current flowing in from power terminal 7 via FET4 becomes minute, decreasing the power consumption.
JP53056934A 1978-05-12 1978-05-12 buffer circuit Expired JPS5846090B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53056934A JPS5846090B2 (en) 1978-05-12 1978-05-12 buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53056934A JPS5846090B2 (en) 1978-05-12 1978-05-12 buffer circuit

Publications (2)

Publication Number Publication Date
JPS54148365A true JPS54148365A (en) 1979-11-20
JPS5846090B2 JPS5846090B2 (en) 1983-10-14

Family

ID=13041340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53056934A Expired JPS5846090B2 (en) 1978-05-12 1978-05-12 buffer circuit

Country Status (1)

Country Link
JP (1) JPS5846090B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0167076A2 (en) * 1984-06-27 1986-01-08 Honeywell Inc. Digital circuit using mesfets
US4712023A (en) * 1985-11-13 1987-12-08 Matsushita Electric Industrial Co., Ltd. Buffered FET logic gate using depletion-mode MESFET's.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0167076A2 (en) * 1984-06-27 1986-01-08 Honeywell Inc. Digital circuit using mesfets
US4712023A (en) * 1985-11-13 1987-12-08 Matsushita Electric Industrial Co., Ltd. Buffered FET logic gate using depletion-mode MESFET's.

Also Published As

Publication number Publication date
JPS5846090B2 (en) 1983-10-14

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