JPS5846090B2 - buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer circuit, and particularly to a buffer circuit using an insulated gate field effect transistor.

Insulated gate field effect transistors (hereinafter referred to as rFETJs) such as MO8 field effect transistors.

) is known as a circuit shown in FIG.

In the figure, 1 and 2 are both N-channel enhanced men 11FETs.

3 and 4 are both N-channel depression type FETs.
, 5 is an input terminal of the buffer circuit, 6 is an output terminal of the buffer circuit, T is a power supply terminal, VDD is a power supply voltage, and E is a ground.

Enhancement type FET1 and depression type FET
3 constitutes a front inverter stage 20, which includes an enhancement type FET 2 connected to the ground E side and a power supply terminal 7.
The depletion type FET 4 connected to the side constitutes an output inverter stage 21.

8,9゜10.11 are all called nodes, and respectively,
8 is the 200 Å power terminal of the pre-inverter stage, 9 is the output terminal of the pre-inverter stage 20, 10 is the gate terminal of FET 2,
11 has a function as a gate terminal of FET4.

Since nodes 8 and 10 are connected, the input signal of the buffer circuit is applied to the gate of FET2, and on the other hand, since nodes 9 and 11 are connected, the output signal of the pre-inverter stage 20 is applied to the gate of FET4. That is, they are each configured so that a signal having the inverted polarity of the input signal of the buffer circuit is applied.

Next, the operation of the conventional buffer circuit shown in FIG. 1 will be explained.

First, a case where the input signal of the buffer circuit changes from low to high will be described.

When the signal applied to the input terminal 5 changes from low to by, the gate voltage of the enhancement type FET 2 becomes by, so the conductance between the source and drain of this FET 2 increases.

On the other hand, since the output of the pre-inverter stage 20 is low, node 9 acts as the output terminal of this pre-inverter stage 20.
is connected to the gate terminal 11.
The gate voltage of ET4 becomes low, and the source-drain conductance of this FET4 decreases.

As a result, the output terminal 6 changes to low.

Next, when the input signal of the buffer circuit changes from high to low, the operation is completely opposite to that described above.

That is, the source-drain conductance of FET 2 decreases, the source-drain conductance of FET 4 increases, and as a result, the output terminal 6 changes to high.

Thus, it can be seen that the buffer circuit shown in FIG. 1 operates as an inverting buffer circuit.

The above explanation is a qualitative explanation of the operation of the conventional buffer circuit shown in FIG. do.

In Figure 2 a, the input signal to the buffer circuit is 5 nanoseconds (ns).
FIG. 2 is a characteristic diagram showing potential changes at each terminal 5, 6 and node 9 when the input signal of the buffer circuit rises linearly at 5 ns, and when the input signal of the buffer circuit falls linearly at 5 ns. The horizontal axis shows time and the vertical axis shows voltage.

In FIGS. 2A and 2A, A indicates the input terminal 5, OUT indicates the output terminal 6, and C indicates the voltage between the node 9 and the ground E.

Note that the circuit conditions and constants of each FET 1 and 2°3.4 used in this analysis are as shown in FIG. 2C and Table 1, respectively.

First, as a circuit condition, the power supply voltage VDD of the power supply terminal T
Both are set to +5V, and the load capacity value of node 9 is 0.2p.
F, the output load capacitance value was 1 pF.

Further, in Table 1, vth is a threshold voltage, and β is a conductance constant.

Here, β is given by the following formula.

As can be seen from the curved line in FIG. 2a, even after the voltage at the input terminal 5 becomes high, the voltage at the output terminal 6 does not become zero.

This is because in the buffer circuit shown in FIG. 1, the gate voltage of depletion type FET 4 cannot be made negative, so this FET 4 cannot be completely shut off.
This is because a large current flows from the power supply terminal 7 through the FET4 and FET2.

For this reason, the conventional buffer circuit shown in FIG. 1 has the disadvantage of high power consumption.

The present invention was made in order to solve the problems of the conventional buffer circuit as described above, and an object of the present invention is to provide a buffer circuit that can reduce power consumption.

The present invention is characterized in that the input signal of the buffer circuit is connected to the gate of the depletion type FET constituting the output inverter stage of the buffer circuit consisting of a pre-inverter stage and an output inverter stage. Alternatively, by applying a signal having the inverted polarity of the input signal through a differentiating circuit, the gate voltage is made to swing to a negative level and the depletion type FET is cut off.

Specific embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing a buffer circuit which is an embodiment of the present invention.

In FIG.
It consists of

Reference numeral 14 denotes a node, which in this case functions as an output terminal of the differentiating circuit 22.

In this example, it is the node 9, which serves as the output terminal of the pre-inverter stage 20, that serves as the input terminal of the differentiator circuit 220.

That is, in this embodiment, the front inverter stage 2
0 and the gate terminal 11 of the depletion type FET 4 constituting the output inverter stage 21.

Next, the operation of the buffer circuit shown in FIG. 3 will be explained.

First, the operation when the input signal changes from low to no will be described.

When the signal applied to the input terminal 5 changes from low to high, the gate voltage of the enforcement FET 2 becomes high, and the conductance between the source and drain of this FET 2 increases.

On the other hand, the gate voltage of the depletion type FET 4 is grounded through the resistor 13 before the input signal is input, and therefore is approximately equal to the ground potential.

When the input signal of the buffer circuit changes from low to high, the output of the pre-inverter stage 20, that is, the input of the differentiating circuit 220 changes from high to low, so that a negative pulse is applied to the node 14 as the output of the differentiating circuit 22. .

Therefore, the gate voltage of the depletion type FET 4 whose gate terminal 11 is connected to the node 14 becomes a negative potential, and the conductance between the source and drain of this FET 4 is
It is much smaller than the conventional buffer circuit shown in FIG.

Therefore, the current flowing from the power supply terminal I through the FET 4 becomes very small, so that the buffer circuit of this embodiment consumes less power than the conventional buffer circuit shown in FIG.

Next, each terminal 5, 6 in the buffer circuit shown in FIG.
The potential changes at the nodes 9 and 14 will be quantitatively explained using FIG.

In Figure 4a, when the input signal rises linearly in 5 ns,
Figure 4 is a characteristic diagram showing potential changes when the input signal falls linearly in 5 ns, where A is the input terminal 5, mouth is the output terminal 6, C is the node 9, and 2 is the node. 1
Each potential of 4 is shown.

Here, the circuit conditions used for this analysis are based on the circuit diagram shown in Figure 4C, and the constants of FETI and 2,3°4 are shown in Table 1 used in the explanation of the conventional example. are the same.

In FIG. 4C, the capacitor 1 constituting the differentiating circuit 22
The values of resistor 2 and resistor 13 were 1.0 pF and 10Ω, respectively.

Also, the load capacity values of node 9 and node 14 are both 0.
It was set to 1 pF.

This corresponds to node 9 in the circuit diagram shown in FIG. 2C in the explanation of the conventional example.
load capacity value is 0. ．． In order to bring the conditions as close as possible to those of 2 pF, 0.2 pF was divided into two parts of 0.1 pF.

Other circuit conditions are the same as those of the conventional example.

As can be seen from curve 2 in FIG.
It can be clearly seen that the potential approaches the ground potential with a time constant determined by the resistor 13 and the resistor 13.

Since this negative voltage is applied to the gate terminal 11 of the depression type FET 4, the FET 4 is completely cut off.

As a result, the voltage at the output terminal 6 becomes zero as shown at the curved line in FIG. 4a.

As described above, in the buffer circuit according to the present invention shown in FIG.
Since the current flowing into the circuit becomes extremely small, it has the effect of reducing power consumption.

Next, another embodiment of the present invention will be described.

Figure 5 is.

FIG. 7 is a circuit diagram showing another embodiment of the buffer circuit according to the present invention.

In this embodiment, the pre-inverter stage 200A has a node 8 which functions as a power terminal, and the output inverter stage 21.
A differentiating circuit 22 is inserted in a connection path to the gate terminal 11 of the depletion type FET 4 constituting the circuit.

Further, a node 9 having a function as an output terminal of the pre-inverter stage 20 is connected to the gate terminal 10 of the enhancement type FET 2.

Therefore, as is easily understood, the buffer circuit shown in FIG. 5 constitutes a non-inverting buffer circuit, that is, a circuit in which the buffer input and the buffer output are in phase.

In this case as well, the insertion of the differentiating circuit 22 has the effect of reducing power consumption in the same manner as described above.

Note that the resistor 13 of the differentiating circuit 22 may be a resistive one such as an FET, and the same effect can be obtained even if it is not necessarily connected to the ground E as in the embodiment.

In addition, in all the above explanations, the load of the pre-inverter stage 20 is composed of the depletion type FET 3, but the load may be a resistance or an enhancement type FET.
Of course, the same effect can be obtained by using the following.

Further, in the above explanation, all N-channel FETs have been explained, but it goes without saying that even in the case of a P-channel FET, the potential polarity can be reversed to that in the above explanation, and the same effect can be achieved.

As described above, according to the present invention, the front inverter stage, the depletion WFET, and the enhancement type FET
In a buffer circuit consisting of an output inverter stage consisting of an ET and an output inverter stage, a differentiating circuit is inserted in the connection path between the input terminal or output terminal of the pre-inverter stage and the gate terminal of the depletion type FET to cut off the depletion type FET. As a result, a buffer circuit with low power consumption can be obtained.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional buffer circuit, Figures 2a and 2 are characteristic diagrams showing the operation of the conventional buffer circuit, and Figure 2C is shown in Figures 2a and 2s. FIG. 3 is a circuit diagram showing the circuit conditions on which the analysis of the characteristic diagram is based; FIG. 3 is a circuit diagram showing an embodiment of the present invention; FIGS. FIG. 4C is a circuit diagram showing the circuit conditions on which the analysis of the characteristic diagrams shown in FIGS. 4A and 4S is based. FIG. FIG. In the figure, 2 is an enhancement type field effect transistor, 4 is a depletion type field effect transistor, and T
is the first constant potential point, 8 is the input terminal of the pre-inverter stage,
9 is the output terminal of the pre-inverter stage, 10 is the gate terminal of the enhancement type field effect transistor, 11 is the gate terminal of the depletion type field effect transistor, 20
21 is a pre-inverter stage, 21 is an output inverter stage, 22 is a differentiating circuit, and E is a second constant potential point. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A front inverter stage that receives an input signal of a predetermined polarity and supplies an output signal of the inverted polarity, a depletion type field effect transistor whose main electrode is connected to a first constant potential point, and one main electrode. and an enhancement type field effect transistor connected to a second constant potential point, are connected in series with each other, and the output inverter stage is configured to derive an output from a common connection point between the other main electrodes of each transistor. , a gate terminal of said enhancement type field effect transistor is connected to an input terminal or an output terminal of said pre-inverter stage, and a gate terminal of said depletion type field effect transistor is connected to an output terminal or an input terminal of said pre-inverter stage, respectively. 1. A buffer circuit comprising: a differentiating circuit inserted in a connection path between the output terminal or input terminal of the pre-inverter stage and the gate terminal of the depletion type field effect transistor.