JPS6442095A - Charge circuit - Google Patents

Charge circuit

Info

Publication number
JPS6442095A
JPS6442095A JP62197866A JP19786687A JPS6442095A JP S6442095 A JPS6442095 A JP S6442095A JP 62197866 A JP62197866 A JP 62197866A JP 19786687 A JP19786687 A JP 19786687A JP S6442095 A JPS6442095 A JP S6442095A
Authority
JP
Japan
Prior art keywords
nmos
terminal
data
constitution
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62197866A
Other languages
Japanese (ja)
Inventor
Fumio Shioda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62197866A priority Critical patent/JPS6442095A/en
Publication of JPS6442095A publication Critical patent/JPS6442095A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To improve the read speed of data of a RAM by connecting the source terminal of a fourth NMOS transistor (TR) and that of a fifth NMOS TR with a negative power terminal. CONSTITUTION:Constitution is added in which the gate terminal of the fourth NMOS TR 8 and that of the fifth NMOS TR 8 are connected with a control terminal 4, the drain terminal of the fourth NMOS TR 8 is connected with a first charging terminal 6, the drain terminal of the fifth NMOS TR 9 is connected with a second charging terminal 7, and the source terminal of the fourth NMOS TR 8 and that of the fifth NMOS TR 9 are connected with the negative power terminal 10. With the size of the first, second, fourth and fifth NMOS TRs 1, 2, 8 and 9, the on-resistances of respective TRs are set. Thus, a data line can be charged to an initial voltage value with which a sense amplifier can be operated at high speed and the data of the RAM can be read at high speed.
JP62197866A 1987-08-07 1987-08-07 Charge circuit Pending JPS6442095A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62197866A JPS6442095A (en) 1987-08-07 1987-08-07 Charge circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62197866A JPS6442095A (en) 1987-08-07 1987-08-07 Charge circuit

Publications (1)

Publication Number Publication Date
JPS6442095A true JPS6442095A (en) 1989-02-14

Family

ID=16381635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62197866A Pending JPS6442095A (en) 1987-08-07 1987-08-07 Charge circuit

Country Status (1)

Country Link
JP (1) JPS6442095A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5847262A (en) * 1996-08-29 1998-12-08 Aisin Seiki Kabushiki Kaisha Impact detecting apparatus
US6072129A (en) * 1997-11-25 2000-06-06 Aisin Seiki Kabushiki Kaisha Impact detecting apparatus
CN102903381A (en) * 2011-07-27 2013-01-30 国际商业机器公司 Sense amplifier

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5847262A (en) * 1996-08-29 1998-12-08 Aisin Seiki Kabushiki Kaisha Impact detecting apparatus
DE19737642C2 (en) * 1996-08-29 2001-10-11 Aisin Seiki Shock detection device
US6072129A (en) * 1997-11-25 2000-06-06 Aisin Seiki Kabushiki Kaisha Impact detecting apparatus
CN102903381A (en) * 2011-07-27 2013-01-30 国际商业机器公司 Sense amplifier

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